Voltage multiplier techniques are extended at medium power levels to larger multiplication ratios. A series of dc-dc converters were built, with from 20 to 45 stages and with power levels up to 100 watts. Maximum output voltages were about 10,000 volts

Harrigill, W. T.

Myers, I. T.

English

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https://ntrs.nasa.gov/search.jsp?R=19780018430 2020-03-22T03:11:25+00:00Z
AA$A TECHNICAL	 NASA TM-78900MEMORANDUM
p	 (NASA-TM-78900)
	 !TEDIUM POWER VOLTAGE
	 N78
-26373ti	 MULTIPLIERS WITH A LARGE NUMbzv (FA(,ES 
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(4&SA)	 H P 11C AC2/MF A01
	 CSCL 10C
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MEDIUM POWER VOLTAGE MULTIPLIERS WITH A
LARGE NUMBER OF STAGES
by W. T. Harrigill and I. T. Myers	 ^ ^^^^gJa
Lewis Research Center	 o	 `-
Cleveland Ohio 44135	 `"	 vt	 d	 ^•'
TECHNICAL PA^.'ER to be presented at the 	 `ra^^Zy^'^^
Power Electronics Specialists Conference
sponsorer l t.;► the Institute of Electrical and Electronics Engineers
Sy: •acuse, New York, June 13-15, 1978
MEDIUM POWER VOLTAGE MULTIPLIERS WITIi A LAW.E. Nt?0ER OF STAGES
w. "r. Harrigill and 1. T. Myers
National Aeronautics and SNdt.+ Administration
Lewis Research Center
Cleveland, Ohio 44175
ABSTRACT
Voltage multiplier techniques were extended
at medium power levels to larger multiplication
ratios. A series of DC-DC converters were built,
with from 20 to 45 stages and with power levels up
to 100 watts. Maximum output Voltages were about
10,000 volts.
I N1'RODUCTUION
Previous work (1-5) has proven that capacitor
diode voltage multiplier (CDVM) DC-DC conversion
with efficiencies up to 96 percent and at power
levels up to 1 kW is possible. The multiplication
factor, or ratio of DC output to DC input voltage
in this previous work was about 8 or 10. This
paper discusses the extension of this muitiplic.a-
tion ratio for medium power multipliers, and ex-
plares large multiplica t lon ratios in terms of
efficiency, weight, and operating characteristics.
Multipliers with twenty to forty-five stages were
examined both analytically and experimentally.
Emphasis was placed on high efficiency and light
weight. Some large multiplication ratio work has
already been reported in the literature (6-11).
However, the converters were of low power and effi-
ciency was not of primary concern.
EQUATIONS FOR LOAD VOLTAGE DROOP,
OUTPUT RIPPLE, AND LOSSES
The voltage multiplier used was of the type
shown in figure 1. The multiplication ratio, at
low power, is approximately equal to the number of
stages. Each stage includes 2 capacitors and 2
diodes. Descriptions of the transistor drive and
control circuits have previously been reported
(1-4) and will not be tepeated here.
The output voltage was determined using tech-
niques previously described by Harrigill and Myers
(1-4), Brugler (12), and Borneman (13). The aver-
age value of the load voltage, V L , is:
i (e)(e + 1)(2s/! + 1/12)
	
V - sV	 LL	 t 	
fC	
(1)
STAR Category 20
1W,
4W
where
s	 number of cmiltlplLer stages
L L	load current
f	 chopping frequency
C	 individual capacitor values
V 
	 imput voltage
For large values of a, the average output voltage,
within a few percent, can be written as:
21Lsd
VL - aVi
	
SfC	 (2)
The first term, sV, is the no load vo:tage and may
be considered analogous to the internal voltage of
a generator. The second term, 21 Ls 3 /3fC, is the
load voltage droop due to capacitor charging losses
in the voltage multiplier
This sclies voltage drop in the voltage
multiplier gives rise to a power loss of 2s 7 1 /3fC.
In addition to the DC output voltage V L , a r pple
voltage VR with a frequency of f is super-
imposed on the output. This ripple voltage has a
peak to peak value of
i (s)(s + 1)
_
VR	
L
 
2fC	
(3)
For large multiplication ratios, the droop voltage,
which is a function of s 3 , is much larger than
the ripple voltage, which is a function of s2.
In addition to the capacitor charging loss,
there are other losses. See reference (2) and
tables I and II. Note that one loss is proportion-
al to if, several are proportional to i L , and
some are independent of i L . This suggeat.e that a
maximum efficiency exists at some load current.
In order to determine this point of maximum effi-
ciency, an expression for efficiency in terms of
i L was formulated and its dervfative with respect
to load current set equal to zero. The efficiency
q is equal to
.o
.o
v
m
1
kk
i	 b
2
e ° Pinput _- pleases 	 (4)
D	
1
input
Pinput ° Iinput Vinput	 ($)
For a well designed voltage inutliplier, the input
current is very nearly equal to the number of
stages s times the load current.
Than
it aV - k isV - k20ViL - k3oviL
°I	 !GiL9V
where k i , k2 and k3 are constants defined by:
ki ° 2CORVf + 2CIRVf + 41bR + 21T,off
	 (7)
!Vg 2VTF 2Vd 2x2 1 IT 1
2
 
ir2 r rb12k2 ° V + V + Vb + 3 1\ ..r /I + q 1\z I (S)YT	 Ib
k	
(a + 1)(2 s/3 + 1/12) 	 28 2	(V)
3	 fCV	 a 3fCV
Where the symbols have been previously defined.
Tile Losses given by sVkl are independent of
load current, the losses given by the k2 term
(sVk2 1L) are proportional to load current, and the
k3 tern losses (2u 31j/3EC) are proportional to the
square of the load current. The efficiency it can
then be written in terns of k l , k2 , k3 and it, as
k
tI .. 1 - it - k2 	k3 1L 	(10)
L
Setting dq/diL ° 0 gives
LkiL(max efficiency) 	 l	 (11)3
and
gmax = 1 - 2	 k, k, - k2	(12)
The trend in the efficiency versus load current
curve, and the variation in efficiency with the
number of stages s, is shown in the experimental
results section.
OPTIMIZING THE NUMBER OF STAGES FOR A
GIVEN OUTPUT VOLTAGE
It is desirable to select the minimum size
(and weight) multiplier for a given application.
The output voltage for u voltage uutliplier of the
type shown in figure 1 was given in equation (1)
as
s(a + 1)(20/3 + 1/12)1Tj
V  ° sV	 fe
The value of capacitunce C requiro ,4 for each
position in the multiplier is:
a(s + 1)(2s/3+ 1/12)4
L
C "
	 f(sV - V 	 (13)
Nuramlly, LL and VL are fixcu by the load. The
frequency f is also fixed or limited by stray
inductances or losses. The number of atages s,
however, may be varied.
The total Capacitance CT is
	
CT ° 2sC, or	 (14)
2s 2 (s + 1)(29/3 + 1/12)1L
	
CT "	 f(SV - V L )	
(L5)
One can now determine the optimum s by differen-
tiation of Op with respect to s, and g utting the
resultant expression equal to zero. From a strict
mathematical standpoin` this is not possible, since
a occurs in discrete, integral values. For this
treatment, however, a will be considered caution-
nos, and the nearest lntebral value taken,
dCT
do
(s+1)^3s+12^+a
	
+i2/+s(s+1^.7^
°i (sV - V )L	 L	 f(SV-VL)2
ILa(s+1)(23 +12)V
-	 f (SV - VL)	 0 (16)
If we take the case with large	 a
3
(sV - VL)2x 2 ° 2	 V, or	 s ° 2
V
V (17)
Substituting into the expression for CT , again
for the case of large 	 a, gives:
27V31
T	 2fV4
and the capacitance per unit stage is
VLi
CT	
2
C ° 2s ° 2
(19)
IV
Since the efficiency of the convertor is iLVL/iinv,
and the input current to very closely equal to
si1,, for the minimum total capacitance case the
efficiency	 IM	is
0
c
0
^	 h
t
S
^1
3a
Vi	 2
	
" IM ®V V 3	 (20)
EXPERIMENTAL IU:ShLTS
A aeries of large multiplication tatLO vultaha
multipliers were built using 10 mlCrufarud Polyvi-
nylidene fluoride capacitors and Coat awLtching
diodes. The input woo 255 V de. Switching wall
provided by npn transistors driven by small pulse
trans farmars. 'rite operational parameters of the
nnultip liur ere given in table III
Alturnate circuit approaches Could have been
taken. For example, a bridge circuit could have
been used for thu owitching transistors, provid ing
double the voltage output with the same number of
stages. However, this would require 4 transiarurs
instead of two. No regulator was used, although
one could have been incorporated, (Sue ref. 3).
'tile purpose of this work was to duvulop Lite tueb-
nology of large multiplication ratio Voltage mu1Li-
plier power vunplies for high power tf tubas; rogu-
latLon, ripple, dynamics reuponso and other re-
quirements will depond upon the particular appli-
cation involved.
Figure 2 gives the voltage ehangu with load
for difterent multiplications. (25 stages means
25 timos multiplication) Calculated load voltages
are given by tlau amid lines. Agreement between
calculated and experimental results are seen to be
reasonably good. Figure 3 shows the efficiency as
a function of load with the number of muleiolier
stages as a parameter. As expected, Lite efficiency
decruaues wLth increasing number of stages, but
still remains intlae middle and high 80 percent
range for reasonable capacitor sizes, As can be
seem from figure 3, 100 watts was near the peak in
the .; Eficiency curve. For applications where some-
what lower efficiencies could be tolerated, it
would be possible to operate the multiplier at
higher power with the sane capacitors. In general,
the ripplu wits small, of the order of one percent,
due to Lite self filtering action of the multiplier
capacitors.
CONCLUSIONS
Medium power, High multiplication ratio volt-
age multiplier 0C-DC converters were inveutigated.
The following. results and conclusions werL obtained
1. A series of capacitor diode voltage multi-
pliers with 20 to 45 stages were built and evalu-
ated, A multiplier with 45 stages and 10,000 volts
output demonstrated 83 percent efficiency at 100
watts output power.
2. Experimental measurements PION analysis
indicates the efficiency of a given configuration
of voltage multiplier increases with, power output,
goes through a maximum, slid decreases at Higher
power.
3, The power level correupooding to the point
of maxLmum efficiency may be varied by varying tine
amuant of capacitance in Lite mulltplLeV.
4. '11le efficiency deetl^asea with I=Mal Lag
ummor Of multiplier atugeu.
5, No fandalnontol limit" to higher Lmltipli-
uutiuna ware found,
6. Large power high mlLipLiCaLlOn ratio volt-
age multipliers can be built, wiLh La component
limitations.
7. Theuretieal predictions of effieiency and
voltage output agree reasonably well with measured
valves
REFERENCES
(1) W. I. Harrigill, Jr. and 1. T. Myeru, '9ltgh
Performance DC-DC Con yers Lun WLth Voltage
MUlL• ipliur9, W1 NASA TH X-71566, presented at
IEEE Power Electronics Specialists Conference,
June 10-12, 1974.
(2) W. T. Hurrig Lil, Jr,and I. T, Myaro, 11RCfl-
elency and Weight of VJltA6L Multiplier 'PypL
Ultra Lightweight DC-DC Converters," NASA TM
X-71735 0 pruseutod at IEEE Power Electronics
Specialists Con Lorcneu, June 9-11, 1975.
(3) W. T. llarrigLll, Jr. and I. 'L'. Nycrs, ""RLgu-
lation of n Lightweight high. Efficiency Capac-
itor Diode Voltage i ,lultiplier UC-UC Convert-
er," NASA 'M X-73427, presented at tlae ISM
Power Electronics Spucialists CanfL•rence,
June 8-10, 1976.
(4) J. J. Much and It, M, Martinelli, "High Fre-
quency Capacitor Diode Voltage Multiplier
DC-OC Converter Development," NASA. CR-1953091
Sep, 1977.
(5) R. M. MartLnullt, "ExtendLd Performance Solar
Electric Propulsion Thrust System Study, Val.
ante Vt Capacitor Diode Voltage Multipl Lur,
'rechnology Evaluation," NASA CR-135281, Sep.
1977.
 
(6) E. CCeinacllLr, "Uber eine Methodc,
Wechselstrum Mittela E1Lktrischen Vuntilu and
Rundunsutorem in Ilachgespanuten Cleichstrova
UsizuwandLiLn, 11 2. Phys.. vol. 4, pp. 195-2051
192L.
(7) P. Lorrain, "On the Design of a Rudiofrcquency
Cachcroft-Walton Aect lerator," Mv. Sri.
Instcunr. vol. 20, pp. 2L6-217, 1949.
(8) E. Everhart and P. Lorrain, "'rite Cockcroft-
Walton voltage Multiplying Circuit," Rev. SOL.
Instrum. vol. 24, pp. 221-226, 1953.
(9) T. P. Nowalk and C. D. lia,fok, "High Voltage
Solar Array Segment," Air Force Auto Propsul-
siun Lab.. 'rR-68-1, 1968.
TARLF. I. - DEFINIrlON OF SYMBOLS
reverse Junction capacitance of diode, F
transistor "off" Junction capacitance, F
unit CDVM capacitance, F
frequency, liz
reverse leakage Curren: of diodes, A
load current, A
transistor "off" do Icakage current, A
nwnher of stages
diode conduction drop, V
transistor drive voltage, V
input voltage, V
transistor average forward conduction
drop, V
chopper transistor current gain
diode switching time, sec
period of diode current, sec
period of transistor input current, act
ttansistor turn on time, sec
CUR
CTR
C
f
LDR
LL
iT,off
a
VDF
V 
VI
VTF
d
tD
'tn
IT
tT
a
4
(10) M. Spretor, "nlode 'rechnology is Key To
Battlefield Intensifier," FUN Feb. 1, pp. 55-
56, 14b9.
(11) J. F. Sutton and J. K. Stern, "Spacecraft High
Voltage Power Supply Construction," NASA 1'N
D-7948, 1475.
(L2) .1. S. Brugler, "Theoretical 11crtormunce of
Voltage Multiplier Clrcults," MF J. Solid-
State Circuits, vol. n, pp. 112-115, 1971.
(11) E. 11. Bomcman, "Roost HiKh-Voltage DC Out-
puts," Flcctror.i. Design, vol. 26, no. 7,
pp. 72-74, 1078.
I'MiU. 11.	 - L06SES IN VOLTAGF. MULT1PLIEK
Lass type Formula for loss
/i1C212Ls1Capacitor charging	 lnss
Diode reverse )unction
losschargang 2sCDRVif
Transistor reverse	 junction
losscharging 2CTRVif
Diode furward conduction
losses 26VDFiL
Transistor	 forward conduc-
tion	 losses tVTPsiL
Diode reverse bias do
leakage losses 4VLiDRa
Transistor 'off" do	 leLk-
age	 losses 2V	 i	 ff1 L 
Transistor base drive loss	 21LVds/N
2
Transistor switenLng losses	 (2n2Vi1Ls/1)(zT/.IT)
2
Diode switching losses	 (it 2VIiLs/1)( D/tID)
TABLE III. - FXPERIKENTAL PARAMFIFR.S
Input voltage	 255 V do
Output voltages	 5000-11,000 V do
Output power	 10-120 W
Switching frequency	 50 kHz
`f
F`
n1
.7
C	 C	 C	 C
4
a^
Figu re 1. - Capacitor diode voltage multiplier.
12
6
a
J
Q
CL
v
U
0	 20	 40	 60	 80	 100
LOAD POWER. W
Figure 2. - Open loop voltage regulation of high multiplica-
tion voltage multipliers.
Ik
90
u
80
zW
.ri li
^ W
TO
5
100	
CALCULATED FIT STAGS
60-----^ --1 - --
20	 40	 60	 80	 100	 120
LOA D. W
Figure 3. -Efficiency of high ML'ltiplication roltaae multi-
pliers.


Medium power voltage multipliers with a large number of stages

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