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Produced by the NASA Center for Aerospace Information (CASI) https://ntrs.nasa.gov/search.jsp?R=19790010025 2020-03-22T01:18:02+00:00Z t - A-CR-161117) DIODE STEP STRESS PROGRAM N79-18196 JANTX1N5554 Final Report (DCA 1•;iability Lab., Sunnyvale, Calif.) 39 P R' f'i/MF A01 CSCI ORA Onclas 63/33 14151 DIODE STEP STRESS TESTING PROGRAM MSFC/NASA CONTRACT NUMBER NAS8 - 3194h FINAL REPORT FOR JANTX IN5554 JANUARY 1979 Prepared For GEORGE C. MARSHALL SPACE FLIGHT CENTER NATIONAL AERONAUTICS AND SPACE ADMINISTRATION Marshall Space Fll ght Center, Alabama 35812 Y1"i9 N'^Ieti,,U OCA RELIABILITY LABORATORY SPECIAL PRODUCTS DIVISION 975 BENICIA AVE SUNNYVALE, CALIFORNIA 94086 JANTX1N5554 FOREWORD I This is a Lammary of the work performed on NASA Contract NAS8-31944. The investigation was conducted for the National Aeronautics and Space Administration, George I C. Marshall Space Flight Center, Huntsville, Alabama. The Contracting Officer's 'Technical Representative was Mr. F. Villella. The short-term objective of this preliminary study of transistors, diodes, and FETS was to evaluate the reliability of these discrete devices, from different l manufacturers, when subjected to power and temperature I step stress tests. The long-term objective is to gain more knowledge of accelerated stress testing for use in future testing of varieties of discrete devices, as well as to determine which type of stress shoulu be applied to a particular type of device or design. I ii I TABLE OF CON 1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . I 2.0 TEST REQUIREMENTS . . . . . . . . . . . . . . . . . 2.1 Electrical . . . . . . . . . . . . . . . . I2.2 Stress Circuit . . . . . . . . . . . . . . 2.3 Group I - Power Stress . . . . . . . . . . 2.4 Group II - Temperature Stress I 2.5 Group III - Temperature Stress II 3.0 DISCUSSIONS OF TEST RESULTS . . . . . . . . . . . . I3.1 Group I - Power Stress . . . . . . . . . . 1. 1. 1 Semtech . . . . . . . . . . . . . . . . . 3.1.2 Micro Semiconductor . . . . . . . . . . . 3.1.3 Statistical Summary - Group I . . . . . . 3.2 Group II - '.Temperature Stress I I3.2.1 Semtech . . . . . . . . . . . . . . . . . 3.2.2 Micro Semiconductor . . . . . . . . . . . 3.2.3 Statistical Summary - Group II . . . . . . I 3.3 Group III - Temperature Stress II 3.3.1 Semtech . . . . . . . . . . . . . . . . . I3.3.2 Micro Semiconductor . . . . . . . . . . . 3.3.3 Statistical Sumn"ary - Group III I4.0 FINAL DATA SUMMARY . . . . . . . . . . . . . . . . . I 5.0 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . APPENDIX A . . . . . . . . . . . . . . . . . . . . IAPPENDIX B . . . . . . . . . . . . . . . . . . . . 2 3 3 3 3 4 4 4 5 6 6 6 6 7 7 7 "'^• ` JANTX1N5554 LIST OF ILLUSTRATIONS I Figure Title Pie 1 Power and Temperature Stress Circuit For JANTX1N5554 . . . . . . . . . . . . . . . . . . 10 I2 Cumulative Percent Failures Versus Junction Temperature, Semtech . . . . . . . . . . . . . . 11 I3 Time Steps Versus Junction Temperature, Semtech . . . . . . . . . . . . . . . . . . . . 12 4 Cumulative Percent Failures Versus Junction Temperature, Micro Semiconductor . . . . . . . . 13 5 Time Steps Versus Junction Temperature, Micro Semiconductor . . . . . . . . . . . . . 14 A-1 SO 6853, Micro Semiconductor, lagnification 8X. 28 A-2 S/N 6856, Micro Semiconductor, Magnification 8X. 28 A-3 S/N 6824, Semtech, Magnification 11X 29 A-4 S/N 6824, Semtech, Magnification 8X . . . . . . 29 B-1 S/N 6916, Semtech, Magnification 1OX . . . . . . 34 LIST OF TABLES Table Title Page 1 Test Flow Diagram . . . . . . . . . . . . . . . 15 2 Parameters and Test . . . . . . . . . . . . . . 16 3 Power Stress Burn-In Conditions . . . . . . . . 16 4 Group I - Power Stress Data Summary . . . . . . 18 5 Group II - Temperature Stress I Data Summary 20 I6 Group III - Temperature Stress II Data Summary. 21 I 7 Final Data Summary . . . . . . . . . . . . . . 22 8 Step Stress Catastrophic Failure Summary 23 I9 Step Stress Parametric Failure Summary . . . . 24 iv I 4 f 0 4 IDA JANTX1N5554 I 1 1.0 INTRODUCTION DCA Reliability Laboratory, under Contract NAS8-31944 I for NASA/Marshall Space Flight Center, has compiled data for the purpose of evaluating the eflect of power/ temperature step stress when applied to a variety of semiconductor devices. This report covers the switch- ing diode JANTX1N5554 manufactured by SEMTECH and MICRO ISEMICONDUCTOR. A total of 48 samples from each manufacturer were submitted to the process outlined in Table 1. In addition, two control sample units were maintained for Iverification of the electrical parametric testing. I 2.0 TEST REQUIREMENTS 2.1 Electrical All test samples were subjected to the electrical tests outlined in Table 2 after completing the prior power/ temperature step stress point. These tests were per- formed using the Fairchild Model 600 high-speed comp- uter-controlled tester. Additional bench testing was also required on the devices. 2.2 Stress Circuit The test circuit shown in Figure 1 was used to power Iall of the test devices during the power/temperature stress conditions. The voltage was set by VF and the I current was varied in order to comply with the speci- fied power rating for this device. At least one of the I devices was subjected to maximum rated power (MRP). All remaining devices were subjected to no less than 904 of MRP. See Figure 1 for load resistance values Iand voltages. 1 WL _ "4hFA JANTX1N5554 I 2.3 Group I - Power Stress I Thirty-two units, 16 from each manufacturer, were submitted to the Power Stress Process. The diodes were stressed in 500-hour steps at 50, 100, 125, 150 and 175 Ipercent of maximum rated power for 2500 hours or until 50% or more of the devices in a sample lot failed.* Electrical measurements were performed on all specified electrical parameters after each power step. See Table 1. 2.4 Group II - Temperature Stress I IThirty-two units, 16 from each manufacturer, were submitted to the Temperature Stress,I Process. Group II was subjected to 1600 hours of stress at maximum I rated power in increments of 160 hours. The tempera- ture was increased in steps of 25 0C, commencing at 750C and terminating at 300 0C or until 50% or more of the devices failed.* Electrical measurements were per- formed on all specified electrical parameters after each temperature step. See Table 1. 2.5 Group III - Temperature Stress II Thirty-two units, 16 from each manufacturer, were Isubmitted to the Temperature Stress II Process. Group III was subjected to 112 hours of stress at maximum rated power in increments of 16 hours. The temperature was increased in steps of 25 0C, commencing at 150 0C and terminating at 300 0C or until 50% or more of the devices in a sample lot failed.* Electrical measurements were I performed on all specified electrical parameters after each temperature step. See Table 1. I * Conditions for failure: I A) Open or short B) Leakage exceeds the maximum limit by 100 times C) Other parameters exceed MIL limits by 50% or more. I 2 L_ ^#O:J JANTX1N5554 I 3.0 DISCUSSION OF TEST RESI'LTS 3.1 Group I - Power Stress I 3.1.1 Semtech. The Semtech sample lot completed the entire 2500-hour Group I Testing with six catastrophic failures. The first failure occurred 500 Yours into the 100% MRP step. Serial number 6825 failed the maximum II?limit. The next failure occurred 500 hours into the 125% MRP step. Serial ,umber 6821 failed the maximum I limit. Serial number 6827 was removed from the Group I Testing 50 hours into the 1500 MRP step as a visual reject due to handling. The next catastrophic failure occurred I 150 hours into the 150% MRP step. Serial numl- r 6906 failed the maximum I limit. The last three failures occurred 250 hours into the 150% MRP step. Serial number 6824 was removed from the Group I Testing as a visual catastrophic failure.* Serial numbers 6902 and 6905 failed the maximum I 12 and minimum V ri , VF2 limits. Typical characteristics of this sample lot's perfor- mance were: 1) The mean value for I changed 2.76uA from an ` initial mean of 163.5nA to a final mean of 2.92WA. 2) The mean value for V r , changed 0.037V from an I initial mean of 1.106V to a final mean of 1.143V. 3) The mean value for V F, 2 changed 75.9mV from an initial mean of 821.9mV to a final mean of 897.8mV. I The control units for this sample lot remained constant throughout the entire Group I 'Testing. I 3.1.2 Micro Semiconductor. The Micro Semiconductor sample lot completed 2250 hours of Group I Testing before the * See Table 8 for explanation. 3 r " 4 IDA JANTX1N5554 lot was stopped because 50% of the devices failed. The first two failures occurred 10 hours into the 175, MRP I step. Serial numbers 6852 and 6859 were removed from the Group I Testing as visual catastrophic failures.* I The next failure occurred 25 hours into the 175% MRP step. Serial number 6853 failed the maximum I limit. I The next three failures occurred 150 hours into the 175% MRP step. Serial numbers 6851, 6858, and 6860 were removed from the Group I Testing as visual cata- strophic failures.* The last two failures occurred 250 hours into the 175% MRP step. Serial number 6854 failed the maximum I limit. Serial number 6856 was removed from the Group I Testing as a visual catas- trophic failure.* Typical characteristics of this sample lot's performance were: 1) The mean value for I II changed 1.82,jA from an initial mean. of 51.90nA to a final mean of 1.87uA. 2) The mean value for VF1 changed 0.024V from an initial mean of 1.033V to a final mean of 1.057V. 3) The mean value for VF2 changed 5.3mV from an initial mean of 841.1mV to a final mean of 846.4mV. I The control units for this sample lot remained constant I throughout the entire Group I Testing. 3.1.3 Statistical Summary - Group I. Table 4 outlines the results of Group I - Power Stress Process for each of the electrical parameters and all measurement points for both Semtech and Micro Semiconductor. 3.2 Group II - Temperature Stress I I 3.2.1 Semtech. The Semtech sample lot completed 1440 hours of Group JI Testing before the lot was stopped because I * See Table 8 for explanation. I 4 rJANTX1N5554 more than 50% of the devices failed. The first failure occurred 160 hours into the 175 oC-temperature step. Serial number 6834 failed the maximum I limit. The next four failures occurred 160 hours into the 2000C- temperature step. Serial numbers 6830, 6910, 6913, and 6914 failed the maximum I limit. The last four failures occurred 160 hours into the 2750C-temperature step. Serial numbers 6828, 6833, 6909 and 6916 failed I the maximum I limit. Typical characteristics of this sample lot's performance were: 1) The mean value for I changed 451.2lpA from an initial mean of 187.8nA to a final mean of 451.40liA. 2) The mean value for VF1 changed .004V from an intital mean of 1.121V to a final mean of 1.117V. The mean value for VF2 changed 7.9mV from an initial mean of 896.3mV to a final mean of 888.4mV. The control units for this sample lot remained constant throughout the entire Group II Testing. 3.2.2 Micro Semiconductor. The Micro Semiconductor sample lot completed the entire 1600-hour Group II Testing Iwith two catastrophic failures. The two failures occurred 160 hours into the 300 0C-temperature step. Serial numbers 6868 and 6877 failed the maximum I limit. Typical characteristics of this sample lot's performance were: 1) The mean value for I changed 144.96pA from an I initial mean of 41.41nA to a final mean of 145.00wii. 2) The mean value for VF1 changed .025V from an Iinitial mean of 1.051V to a final mean of 1.076V. 3) The mean value for VF2 changed 9.2mV from an Iinitial mean of 890.1mV to a final mean of 899.3mV. 5 JANTXIN5554 The control units for this sample lot remained constant throughout the entire Group II Testing. I3.2.3 Statistical Summary - Group I::. 'fable 5 outlines the results of Group II - Temperature Stress I Testing for each of the three electrical parameters and all measure- ment points for both Semtech and Micro Semiconductor. 3.3 Group III - Temperature Stress II 3.3.1 Semtech. The Semtech sample lot completed 48 hours of Group III Testing before the lot was stopped with one catastrophic and eight parametric failures. The cata- strophic failure occurred 16 hours into the 200 oC- temperature step. Serial number 6840 failed the maximum I limit. Typical characteristics of this lot's performance were: 1) The mean value for I changed 15.411,A from an initial mean of 202.OnA to a final mean of 15.611iA. 2) The mean value for VFl changed .030V from an initial mean of 1.119V to a final mean of 1.149V. 3) The mean value for V F2 changed 16.3mV from an initial mean of 881.6mV to a final mean of 897.9OmV. The control units for this sample lot remained constant throughout the entire Group III Testing. 3.3.2 Micro Semiconductor. The Micro Semiconductor sample lot completed the entire 112 hours of Group III Testing with no catastrophic failures. Typical characteristics of this lot's behavior were: I1) The mean value for I changed 4.6811A from an initial mean of 73.13nA to a final mean of 4.75UA. I2) 'The mean value for VFl changed .013V from an I initial mean of 1.044V to a final mean of 1.057V. 6 k 4 DA Pr JANTX1N5554 I 3) The mean value for VF2 changed 1.8mV from an initial mean of 8f)6.OmV to a final mean of 887.8niV. The control units for this sample lot remained constant throughout the entire Group III Testing. 3.3.3 Statistical Summary - Group III. Table 6 outlines the results of Group III - Temperature Stress II 'Testing for each of the three electrical parameters and all measurement points for both Semtech and Micro Semi- conductor. 4.0 FINAL DATA SUMMARY Table 7 statistically summarizes the change in the mean value from the zero-hour data to the final data. The graphs of Figures 2 and 4 plot the cumulative percent failures versus the temperature stress level `.or Group II - Temperature Stress I, and Group III - Temperature Stress II. The graphs of Figures 3 and 5 plot the time step for Group II (160 hours) and Group III (16 hours) versus the temperature T 1 and T 2 calculated from Figures 2 and 4. Tables 8 and 9 summarize the failures encountered for all three stress groups. The failures are separated into two categories: catastrophic fail- ures in Table 8 and parametric failures in Table 9. The data From Table 8 was used as a source for the graphs in Figures 2 and 4. Figures 2 and 4 were used as a source for the graphs in Fig. 3 5 respectively. I Junction temperature is plotted on an inverse hyper- bolic scale. I 5.0 CONCLUSIONS I An overall view of the test results indicate that the Micro Semiconductor diodes are mere durable than the 7 JANTX1N5554 I Semtech diodes. In both Group II and III Tests, the MSC lots had fewer failures which also occurred later in the testing than the Semtech lot. 7n the Group I Testing the MSC lot was stopped 250 hours before the end of the process but all eight failures occurred in the 175`x. MRP step. The six Semtech failures occurred in lower MRP steps. Failure analysis was performed on Group I and Group II because of an apparent failure mode throughout the testing. Almost all of the Semtech failures and many of the MSC failures were due to excessive I leakage. In addition, the remaining MSC devices which failed were still within the electrical limits of the test when they became visual failures due to loss of their anode leads. This suggests these structural failures were caused by exceeding the thermal design limits of the parts. In the case of the Semtech parts, the curve trace at peak inverse voltage (PIV) indicates a condition of surface instability due to contaminiation. This con- tamination can move under the influence of temperature and bias. The analyzed sample are 1 rejects because their breakdowns have drifted below 1000 volts. The hard, stable breakdown of these sample indicates that there is no junction damage. The most probable cause of the lowered breakdown voltage is a change in the concentration of surface impurities on the P-N junction. when there is a slight concentration of impurities of the same polarity as the high resistivity side of the I junction (not sufficient to cause inversion) then that resistivity will be raised. This in turn will raise the breakdown voltage. Upon migration of these pro- ftective charges away from the vicinity of the junction, 8 X 10 -5 eV/ oK J Q T2+273 Temp Stress I = 1 Temp Stress II = of 16% failure for of 16% failure for eV 60 firs. 16 hrs. Group II. Group III. ap WF JANTXlN5554^..I the resistivity and the bre.ikdown will fall. The hard breakdown curves of these samples taken together with their acceptable leakage levels at 1000 volts bias during earlier tests, suggests that the surface charge migration mechanism as described above was the cause of the failures. A plot showing the Cummulative Failure distribution for Groups II and III Testing was drawn for the Semtech Isample lot (Figures 2 and 3), but a complete graph could not be drawn for the Micro Semiconductor sample lot because of are insufficient number of failure points in the Group II Testing and an absence of failure points in the Group III Testing. Figures 2 and 3 display the Semtech-sample lot used to calculate an active energy of 2.42eV. A biuken circle around a marked point on the graph indicates a freak failure not calculated as as part of the regression line. A solid circle around a marked point indicates and isolated failure point. The regres- sion line was calculated using the least squares me thod . The activation energy was calculated from the formula: 8.63 E = in tl 1 _ c 2 T1+273 where: t = step of Group II t 2 = step of Group III T 1 = temperature in 0 T 2 = temperature in 0 9 fIC^\ SWITCHING U = i6 v^ L f R 1 = 1.V/ I + 1% Pd = IE FIGURE i Power and Temperature Stress Circuit 10 I JAN'I'X1N5554 rn m (1 IT U0 ,4 cr; 4-) Z M S4 v J vWUE- O^G" c 41 U h Q [l 8 `^ m ^- -- in wpm r le ,1ANTX1N5554 ti4 w0 koO u v v ^o v o H 0 0 [n 0 an0 I` LO N 0 f- O) c ti O^ N 0 ti NLn ^ qT V q E ^M^ M M N N N N — — — — r 0-0 (Do) 3aniV83dW31 NOI1ONnr 12 O u 0 n Z W ^a 0 U I JANI'X1N 5554 a) Qi s-. O 1.1 to a ^ U^ o / U E- h i CE-.U i GU i O i U H i i i I C I +^ f1^ ^ O H >~ t~ H C) C m A G1 \ ►. U •^ O Q II II O •.4 O r. N w I G 44 04 .Q O 44 (rj 2 —4 In ^4 a !~ +)nc:10rt1~ 0-4 ra U ••I U •1-4 O 0 I~ ro H lJ a. H (d W F-4 r H H Q C1 ^^ '^.. _ O W a 14 F. . 41 0 0.'U ::j 7 r+ II II O C) ^4 O 'L3 >4 :1 C1 14 C1 rJ -+ n;L 0 rC5 Er E+ H O O it 0 u U 1. CJ I-4 OO ` 4-1 ...^ nC W v D J vH O to ~ 'r •^ W C p W ^-+ W ^ ^ ^ p > a m o : U ro w LO v U N l4 U a4 C) Inyi ri a c: _ U O ti O N O f- O V O ti O NLO O i LO tt tt M M M M N N N N Li 0 (:Do) 3aniV83dW31 NOliONnr * .i^ + .mr; zw ® J^ 13 IF 1 l I i I O Adh ^'Aft ^5 0.50 MRP 500 Hours Note 1 TA = 75 °C L = !60 Hours TA = 150°C t = 16 Hours 1.0 MRP 500 Hours Note 1 1.25 MRP 500 Hours Note 2 T A = 125 °C t = 160 Hours TA = 100°C t = 160 Hours TA = 175°C t = 16 Hours T A = 200°C t - 16 Hours Ilibe\ JAVTX1N5554 'I I . LiL, 1 'PEST F1')W DIAGRAM 1;1 1 T I AL ELE':TR I CAL TESTS Per Table 2 (2),: i Non-Operating Control Group 16)' Power Stress T A = 2.5°C (16) Temperature Step Stress I 100 Percent MRP Note 3 ( 1 6) Temperature Step Stress II 100 Percent MRP Note 4 1. 5 MRP 500 Hours 25°C Steps 25°C Steps Note 2 1.75 MRP TA = 300°C TA = 300°C 500 Hours t = 160 Hours t = 16 Hours I, Note 2_. Quantity per manufacturer (Senttech and Micro Semiconductor) NOTES: 1) Electrical measurements per Table 2 were made at 50, 150, 250 and 500 hours. 2) Electrical measurements per Table 2 were made at 10, 25, 50, 150, 250 and 500 hours, 3) Electrical measurements per Table 2 were made at the end of each 160 hours. 4) Electrical measurements per Table 2 were made at the end of each 16 hours. l^ 04 IPA JANI'X1N5554 f TABLE 2 Parameter and Test Conditions I I SPECIFICATION CATASTROPHIC* LIMIT LIMIT PARAMETER CONDITIONS MIN MAX MIN MAX UNIT R 1.0 100 IAA I p VR=1000V v FI .6 1.3 .3 1.95 V(PK) I r @ I F=9.0(PK) PULSED VF2 .6 1.2 .3 1.8 V @ 1 0 =2.OA NOT PULSED In addition, any open or short shall be considered catastrophic r TABLE 3 Power Stress Burn-In Conditions VF=1.OV I F = p D 1.8A 50 3.6A 100 4.5A 125 5.4A 150 6.3A 175 16 JANTX1N5554 NOTE FOR TABLES 4 THROUGH 7 The minimum/maximum initial and final data generally have an absolute accuracy of ± 1% of the reading and ± one digit except for readings greater the 9.99mA which have an absolute accuracy of ± 2% of the reading and ± one digit. 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(Z' ^v O O C a U W N N ►- N n U O U 1(1^ U O^ U S^ U $ N U N N U O N U N N U O f'7 W H O I I I 1 1 I I I I 1Z m LL O O Cl O O O 0 O O CO 1 W O I I I 1 Q I I I Q 1 c Q z s LL } U J O O O G O O ^- a t L L a L t L N W L ppc O p O 8 t O O O N L r L +-'y C N O111 Ln N tea, N N Pape i , 4FUN JANTX1N5554 I I I APPENDIX A I Failure Analysis I Power Stress I I I I I I 25 -c E C MFSC S 'PE"-STRESS '1'F:S'P A :^=f7jj#11 FAILURI flllLlTI JAfq'I'X1N55541)I131)ES Date 2 November 1978 I J/N 2CN242- 23A P/N 1N5554 MFR Micro Semiconductor Limit: Limits: 'AILURE VERIFICATION: 1.OtiA Max. 0.6 - 1.2 V PIV Ir(a Vf(a Initial -volts- 100OV.d • 2.0 A Rej . fo, dc Test Seq. Initial S/N No.: Rej. for- 6853 210 (RI 0.60 MP-23 I 6856 1100 2 uA 0.73 MP-25 I ,859 1100 0.5 uA 0.65 MP-22 Lead Off i USUAL INSPECTION. IAll three Hicro Semiconductor samples have lost their external paint tnd have a burnt area on one lead where it was held in the burn-in clip. S/N 6853 has cracked glass (see Figure A-1). S/N 6856 has lost its external anode lead (see Figure A-2). I QF .^ F- -h trace present. Cannot meet stated test conditions. (Leaky) :.th F' `race very leaky. i = drift H = hysteresis Inv = inversion R = resistive 5 = soft Uns = unstable MFSC STEW-STRESS TEST - I 7CT M M I A"'AL . . DTODES P/N 11`15554 MFR Semtech JANTX1N5554 Date 2 November 1978"iA J/N 2CN242-23A Limit: Limits: "AILURE VERIFICATION: 1.Ou A Max. 0.6 - 1.2 V PIV I1`@ V @f Initial -volts- lOOCV.dc 2.0 A Red dc Test Seq. Initial S/N No. Pei. for ,1824 1100 1.OuA 0.70 MP-19 I + I 6902 940 0.65 MP-20 I ^690C 900 _ _ _ 0.62 MP-20 I — "ISUAI, INSPECTION. All three Semtech samples have lest their external paint and have a burnt area on one lead where it was held in the burn-in clip (see Figure S/N 6824 has lost its external anode lead (see Figure A-4). h FE !race present. Cannot meet stated test conditions. (Leaky) "FE trace very leaky. ID = drift N = h y steresis Inv = inversion R = resistive S = soft Uns = unstable 2 r ' 4 NWAN FIGURE: A-1 S/N 6853 Micro Semiconductor Sample Showing Cracked Glass, 8X I FIGURE; A-2 S/N 6856 Micro Semiconductor Sample Showi ny Lost Anode Tread, 8X (Similar to S/N 6859) JANTXIN5554 28 ,NOVA JANTXIN5554 FIGURE A-3 SIN 6824 Semtech Sample Showinq Anode Lead Melted at the Point of Contact to the Burn-in Clip, 11X FIGURE A-4 SIN 6824 Semtech Sample Showing Lost Anode Lead, 8X 29 rJANTX1N5554 I CONCLUSIONS Micro Semiconductor I SIN 6856 and 6859 were still within the electrical limits of the MSFC test when they became visual failures due to loss of their anode leads. This suggests that these structural failures were caused by exceeding the thermal I design limits of the parts. SIN 6853 has a damaged junction due to electrical over- stress, and cracked glass. ISemtech SIN 6824 was electrically acceptable to the MSFC test limits when its lead detached due to exceeding the meltinq point of the lead connecting metal. SIN 6902 and 6906 failed for excess reverse leakage current because the peak inverse voltage (PIV) of both samples is less than the 1000-volt test condition. (See electrical data in Failure Verification section above.) The hard, stable breakdown of these samples indicates that there is no junction damage. The most probable cause of the lowered breakdown voltage on these samples is a Ichange in the concentration of surface impurities on the P-N junction. When there is a slight concentration of impurities of the same polarity as the high resistivity side of the junction I(not sufficient to cause inversion) then that resistivity will be raised. This will in turn raise the breakdown I voltage. Upon migration of these protective charges away from the vicinity of the junction, the resistivity and the I breakdown will fall. 30 iIICs\ JANTX1N5554 The hard breakdown curves of these two samples, taken I together with their acceptable leakage levels at 1000 volts bias during earlier test sequences, suggests that the surface I charge migration mechanism, as described above, was the cause of the failures. I I I I I I I I I I I I 31 1041h.^ JANTXIN5554 APPENDIX B Failure Analysis Temperature Stress 32 POA MSFC STEP-S'1t'ESS TEST F7^TLTTTtT 11^I7CT.I'ST^ DIM!; J/N_ P/N 1N5554 MFR—Somte FAILURE: VERIFICATION: Limit: I,imits: --- - JANTXIN5554 Date irC^ Vf -vol ts- 1000 V.d 2.0 A do (cQi.i I 1040 LIQZf] (flr ILLI. 940 Initial Rej. Q Test Seq. Initial I'Jo.: Re j . for ,AU_7 T D F of ti T KID-? T VISUAL INSPECTION. All the samples have lost their external paint. There are no other significant defects (see Figure B-1). CONCLUSIONS. IThe action of the curve trace while measuring PIV on these parts indicates a condition of surface instability due to contamination which can move under the influence of temperature and bias. I These samples are I rejects when measured at 1000 volts because their breakdowns have drifted below 1000 volts. The surface action I which resulted in this voltage drift is the same as that described in Appendix A. J C: "FE trace present. Cannot meet stated test conditions. (leaky) :hFE trace very leaky. I) drift H = hysteresis Inv inversion R = resistive S soft Uns = unstable to AII:A JANTX1N5554 i FIGURE 11-1 S/N 6916 Typical Semtech Diode, 1OX .1 C. 34

Diode step stress program for JANTX1N5554

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