The Automated Array Assembly Task, Phase 2 of the Low Cost Silicon Solar Array Project is a process development task. The contract provides for the fabrication of modules from large area tandem junction cells (TJC). During this quarter, effort was focused on the design of a large area, approximately 36 sq cm, TJC and process verification runs. The large area TJC design was optimized for minimum I squared R power losses. In the TJM activity, the cell-module interfaces were defined, module substrates were formed and heat treated and clad metal interconnect strips were fabricated

Carbajal, B. G.

English

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https://ntrs.nasa.gov/search.jsp?R=19790015353 2020-03-21T23:50:52+00:00Z
DRL-10
DOE/.JPL 954881-79-5
AUTOMATED ARRAY ASSEMBLY
PriASE 2
Texas Instruments Report No. 03-79-28
Quarterly Technical Progress Report
January-March 1979
Bernard G. Carbajal
April 1979
JPL Contract No. 954881
Texas Instruments Incorporated
P.O. Box 225012
Dallas, 'Texas 75265
,-
(NASA-CR-1585(7)
	 AUTCMATEL AFRAY ASSEMPLY,
PHASE 2 CuartFrly Technical Frcgress
F.eFo[t, Jan. - Mar. 1979 (Texas Instruments,
Inc.)
	 17 p HC A02/"7F A01
	 C SCI 10A
N79-23524
Tlnclas
G3/44 25193
This work was performed for the Jet Propulsion Laboratory, California
Institute of Technology, under NASA Contract NAS7-100 for the U.S.
Department of Energy, Division of Solar Energy.
The JPL Low-Cost Solar Array Project is funded by DOE and forms part
of the DOE Photovoltaic Conversion Program to initiate a major effort
toward the development of low-cost solar arrays.
I ^^
TABLE OF CONTENTS
SECTION TITLE FAGS
I. INTRODUCTION 1
II. TECHNICAL DISCUSSION 2
I.	 Large Area	 Tendem JUnCtiorl Cell
1.	 Cell	 Design 2
2.	 Process Verification 1
I I .	 Tandem ,Junction Module :1
1.	 Define Celi	 -	 Module 5
2.	 Modify Tooling 5
3.	 Define beat Treatment e1
4.	 Porcelainize Substrates 0
S.	 Design and Form Bus Bars 6
6.	 Solder	 Fixture 10
III. CONCLUSIONS AND RL•'COMMENDATIONS 12
I\r . NEW TECHNOLOGY 13
V. PROGRAM SUMMARY 4
LIST OF ILLUSTRATIONS
FIGURE
	 TITLE
	 PAGE.
1. TJC METAL PATTERN
	 3
2. TOP VIEW OF SUBSTRATE BLANK
	 7
3. FORMED SUBSTRATE
	 g
4. CROSS SECTIONS OF CLAD METAL INTERCONNECTS
SOLDERED TO TJCs.	 11
S.	 WORK PLAN STATUS	 15
ii
SECTION 1
INTRODUCTION
The Automated Array Assembly Task, Phase 2 of the Low Cost
Silicon Solar Array (LSSA) Project is a process development task.
This contract provides for the fabrication of modules from large
area tandem junction cells (TJC). The key activities in this
contract effort are a) Large Area TJC including cell design, process
verification and cell fabrication and b) Tandem Junction Alodule
(TJM) including definition of the cell-module interfaces, substrate
fabrication, interconnect fabrication and module assembly. The
overall goal is to advance solar cell module pc • ocess technology to
meet the 1986 goal of a production capabity of 500 megawatts per
year at a cost of less than $500 per peak kilowatt. This contract
will focus on the Tandem Junction Module process.
During this quarter, effort was focused on the design of a
large area, -36cm 2 , TJC and process verification runs. The large
area TJC design was optimized for minimum I R power losses. In
the TJM activity, the cell-module interfaces were defined, module
substrates were forined and heat treated and clad metal interconnect
strips were fabricated.
	
All activities :ire onor ahead of schedule.
1
i^
1
SECTION II
E	 ^
TECIIN ICAI. 1)1 SCU SS I ON
Both major task areas are in progress. 	 A brief dest-ri1)t,on of tl^
activities in each area follows.
I. Large Area Tandem Junction Cell
1.	 Cell Resign
A cell design has been chosen on the basis of minimum pottier
loss that consists of two interposed finger patterns, one i:, the N-
contact and the other is the P-contact. The N+ and P+ hond pads
are located along opposing sides of the cell. The contact Fingers
will be stepped in width to accomodate increasing current as the
finger appraoches the bond pad area. 'Trunk lines will not he used.
A schematic of the cell contact pattern is shown in Figure 1. The
stepping of finger width is shown in the figure.
Finger widths and spacings have been set. A v%orst case loss
anal y sis has been calculated for series resistance and P area on the
back side. Total series resistance losses are projected to be 4 - 77
depending on Ag plating thickness and P+ contact resistivity. The
corresponding limits on fill factor are calculated to be 0.78 - 0.75,
assuming a low nKT current.
I 2 R power losses are calculated using; equations 1 and 2 to
calculate the fractional loss in the P+ fingers and in the base,
respectively.
F	 = J, dm L 2 	 +	 J-- d m 1,2	 1T	 24 V oc 112	 ( )
and
F	 =	 JS `- d2	 Ps (base)B	 12-- Von.
where
J sc = short circuit current density = 0.035 A/cn12
d	 = center-to-center finger spacing = .102 cm
m	 = metallization resistivity (Q/o) _ .005 Q2/cj
L	 = finger length - 6 cm
T I = finger width narrow section = .0076 cm
(2)
2
ri
i
i
O
I
'4
I
i
^, t
I
4616-04
FIGURE 1. TJC METAL. PATTERN
3
i1
T2 =
	 finger width wide section = .025 , 1 cni
Voc = Open circuit voltage = 0.6 V
Ps
 = Base sheet resistivity (Q/o) = 533 Q/o
The fractional power loss in the fingers, F F is -1.7°, and in the
high resistivity base region is --2.6 0  for this design.
	 Other
design options using internal plated metal bus bars would give
larger fractional power losses.
Bond. pad sizes were chosen to facilitate module interconnections
using condendation or
	 IR solder techniques and clad metal inter-
connect ribbon. Bond pad spacing from the cell edge has been defined.
The N+ bond pad is located further from the cell edge than the P+ bond
pad.	 'this is to protect the N+/P jL,ction from possible damage in
the scribe and break operation.
This ce^l design uses the relatively massive interconnect har
to reduce I R power losses in the bonding pad along the cell edge.
In this fashion, normal power losses associated with the plated
metal bus bars are eliminated.
The design has been coded and plotted at lOX for visii;il check
and verification. The test sites around the edges of the wafer
allow testing of the N+ and P+ sheet resistivity, contact res i st i c- i t v
and plated metal sheet resistivity were checked at 100X.	 ("1atir: 111r1titers,
at 10X, have been obtained and photomasks are on order.
The design activity will be complete as soon as photomasks are
received.
2.	 Process Verification
Process verification test lots are being rLui on 2 x 2 cm TJC's.
Probe testing is done before sawing into squares by usin g hack side
illumination (the lioht shines between the metal contacts). Only
preliminary conclusions can be drawn from these probe tests.
>41
In the variations on back side boron
1 x 10 14 atom/cm 2 dose, appears best wit
S x 10 13 atom/cm 2 and 2 x 10 13 atom/cm2,
short circuit current. These cells were
were thermal compression bonded to allow
measurements.
implant, the standrrd process,
h the reduced dose levels,
both giving about 25°; lower
sawed and gold ribbon tabs
normal front side i 1 111111inatio11
Alloying Al P+ contacts at 650 0 C or 850°C gives virtually identical
results at backside probe. Both temperatures are effective.
4
•r
1
-ift,
Front side illumination after attaching gold tabs gave the
following results.
	 In thy back side boron implant experiment
only the 1 X 014 atom/cm implant gave good results Voc = 0.;86V,
J sc n 3SmA/W at AM1. The implants at 2 and 5 
2 
10 13 	atom/c-m--
gave eery poor results, V oc -0.5 V, Jsc I0mA/cm indicating a severe
lifetime degradation during processing. These experiments are being
repeated.
Front side illumination tests on cells where the I'+ region has
created by alloying evaporated Al at 850°C and 6S0°C showed that the
850°C alloy condition gave slightly getter results with Voc risiHv to
O.S05V and Jsc increasing to 38mA/cm- at AM1. The 850°C allo y
 step
will he considered for inclusion in the baseline process.
The lot of TJC's run on 1SOpm thick material show very poor
response similar to the lower boron implant cells. The very low
photoresponse indicates a severe lifetime degradation. The cause
of this degradation is not known at this time.
Contact resistivity on the P+ regions was measured alter alloying
Al at 6S0°C and 850°C. The concentric ring pattern described in
earlier reports on this contract was used. Contact re s istivity between
the evaporated Ti-Pd-Ag contact metallization and the allo yed Al P+
layer is shown below.	 In all cases 4000A of evaporated Al was used.
6SO 0 C/30 min.	 850°C/30 min.
Pc (Q-cm 2 )
	
2 - 4 x 10'3
	
1 - 2 x 10-'
Further sinterin of the contacts at 4S0°C did not appreciably
change Pc. The Pc obtained with the 850 0 C alloyed Al region is
accpetable for cell fabrication.
II. Tandem Junction Module
1. Define Cell - Module
A design review was held in ,January to review and define the
critical .items in the cell and module design. The module will he a
parallel (S) - series (6) array of 30 cells. The external cell
dimension, a nominal 6.2 cm, is shown in figure 1. The N+ and P+
bond pads will be 0.127 cm wide with a 0.025 cm separation from the
op posite conductivity metal finger.
The clad metal interconnect strip will span from the P+ bond paid
on one cell to the N+ hones pad on the next (series) cell	 The inter-
connect will he designed to fall 0.025 cm from the inside dimension of
the bond pad to allow for the solder fillet. 	 The connection will he
made using condensation or infrared soldering.
2. Modify fooling
An analysis of the minimodule size indicates that embossing is not
necessary to assure substrate rigidity. 	 On larger suhstrates, 1.2x O.b m,
embossing would be recommended. The embossed groove also provides
;I
5
I'
recess for the back side interconnects.
	 In the series - paraII e 
configuration chosen for this work, the interconnect thii Lne y s: is
only 0.002 inch (0.0051 cm) and recessing is unnecessary. There lOrc
tooling modification was not necessary and was c li m i n:ited.
Sheet
	 steel
	 has been cut ,	 Figure 2,	 ankl	 f(II'MCd tO	 !:hJJW.
	
TwcIt1
(20)	 substrates were formed using 20 gaut,e	 (O.OS59 inkli,	 ti.wIl.'	 (m)
cold rolled steel
	 and twenty	 (20)	 substrates wcrr formed	 iisilig
gauge
	 (0.0299
	
inch, 0.0759	 cm)	 cold rolled
	
ti10e1 . Top	 ;Ind	 fr^nt	 i^n^
of the	 formed cold rolled
	
steel	 for the	 substrate ;11-e	 shown	 in	 Figure	 S.
3. Define Heat Treatment
Ten (10) formed substrates of each gauge cold rolled steel were
stress relieved at 600°F (316°C) for one hour in air. The substrates
were shipped to Ervite Corporation, Erie, Pennsylvania, for porcelainiz-
ing. Evaluation of the heat treatment will be made after porcelainizing.
4. Porcelainize Substrates
See paragraph II. 3 above. The porcelainized substrates should he
received in April.
S. Design and Form Bus Bars
As demonstrated earlier in this contract, copper/Invar/coppe-
laminates can be fabricated to match the thermal expansion coefficient
of silicon. The tandem junction module interconnect scheme will use
thin ribbons of this clad metal material. Copper/Invar/copper his
been bonded with a 12.5/75/12/5 ratio, and rolled to a thickness of
0.0102 cm. The bus bar material will subsequently be rolled to
final thickness of 0.0051 cm.
The minimum allowable bus bar thickness can be calculated by
defining the minimum allowable power loss ill 	 bus bar.	 If we
allow a to I 2 R power loss and assume a cell output of 1.OA at 0..-)V,
then minimum bus bar thickness is calculated as follows:
AP = I2Rc	 (3)
where
AP = allowable loss = .01 x 1.0 x .5 = .005W
I = Cell output
Rc = Resistance of clad bus bar
then
0.005 ^'+' _ (1.0) 2 Rc
Rc = .00S  S2	 i' •	 r r^tlP^.l~.
Of
bI
6
2 -
U F
2 u
a v
^ o
^n c
0.501NCH----bI	 ^---	 0.50 INCH
FIGURE 2 TOP VIEW OF SUBSTRATE BLANK
TOP VIEW
X—u EZ M
^ N
O O
ui a
U
13.36 INCH
(33.93 cm)
1.00 INCH
FRONT VIEW	 12.54 cm)
FIGURE 3.	 FORMED SUBSTRATE
7A
The resistance of the composite clad metal ^on,114 , 101 • k.in I)(•
calculated as a set of parallel layers
a
1 = 1 + 1 • •
	
1
7Tc R l R,	 Rn
where R I , R 2 ••••Itn
 are the respective resistances of the clad
metal layers.
By combining the top anti bottom copper layers into one terin
we get.
1 = 1	 + 1	 (4)
Rc Rcu RInvar
or
I = IV x t `11	 +	 IV x t Invar	 (S)
Rc PC  x I.	 PI nvar x L
where
W	 = width of bus bar = 4 cm
L	 = length of bus bars = 0.1 cm
t cu	 = Total copper thickness = 0.25 'I'll
t Invar = Invar thickness = 0.75 TB
Pcu	 = Resistivity of copper = 1.7 x 10 -6 S2-cm
Plnvar = Resistivity of Invar = S.0 x 10 -5 S2-cm
T B	= 'Thickness of bus bar
Solving for T B we get
TB	= 6.2 x 10- S cm
"Therefore one would expect a negligible	 loss irn the bus bar
interconnects of S.1 x 10- 3 cm thickness.
9
6. Solder Fixture
ith bus bar thickness of
x 2 cm TJC's.	 Cross
shown in figure 1. No
with the bond integrity
thin, 0.0051 cm, clad
Soldering evaluations were conducted w
0.025 cm, 0.0102 cm, and 0.0051 cm using 2
sections of the soldered interconnects are
problems were encountered nor are expected
at the bus bar - plated Ag interface. The
metal interconnects perform as expected.
A vacuum chucked soldering fixture has been designed fur module
fabrication. The fixture is -700 complete and should he ready for
evaluation as soon as large area TJC test samples are ready.
10
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SECTION III
CONCLUSIONS AND RECOMMENDATIONS
• Solar cell - module interrelations were defined prior to Finalization
of the T,1C or TJNI design. The TJC will have N+ and P+ metal contact
pads, one each, on opposite edges of the cell. the cell-to-cell
interconnects will provide the collecting bus bar function.
s In tte TJC structure, a back side boron implant dose of I x 1014
atom/cm appears to be near optimum as a psuedo back surface field.
• Sample TJDts will contain 30 cells in a parallel (S) - series (6)
array. Interconnection will be made using copper clad Invar ribbon.
The clad metal ribbon thickness will be 0.005 cm. Soldering experi-
ments have shown that the ribbon can be readil y soldered to p ated
Ag contacts.
12
SECTION IV
NEW TECHNOLOGY
No areas of new technology were identified thi quarter.
13
SFCT I ON V
PROGRAM SUNDIARY
Figure S shows the current work plan status. All sciredulcd
activities are in process. No prohlems are apparent at pres(nt
that will prevent attaining the indicated milestones.
I
14
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15


Automated Array Assembly, Phase 2

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