The implementation of DDLTRN and DDLSIM programs on SEL-2 computer system is reported. These programs were tested with DDL descriptions of various complexity. An algorithm to synthesize the combinational logic using the cells available in the standard IC cell library was formulated. The algorithm is implemented as a FORTRAN program and a description of the program is given

Shiva, S. G.

English

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LOGI IC SYNTHESIS FROM DDL nrGra
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SAJJAN G. SHIVA
Computer Science DepartmenL
THE UNIVERSITY OF ALABAMA IN HUNTSVILLE
Huntsville, Alabama 35807
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(NASA-C8- 161386)
	LOGIC SYNTHESIS FROM DDL
	 N62-20905
DESCRIPTION
	 Quarterly Progress Report, 1
Oct, - 31 Dec. 1979 (Alabama Univ. in
If untsville.)	 18 p HC A02/M:F A01
	 CSCL 09b	 Unclas
G3/61	 16743
January 1980 a
Fifth Quarterly Progress Report y
October 1, 1979 - December 31, 1979
Contract	 NAS8-33096
"DESIGN SYNTHESIS OF DIGITAL SYSTEMS"
George C. Marshall Space Flight Center
Alabama, 35812
r^	 APr44'
	 K^C^lY^D A
4.	 AC	 01G!- 1W
_. I
EFORWARD
;E
This is a technical summary of the progress made
since October 1, 1979 by The University of Alabama
in Huntsville towards the fulfillment of the con-
tract NAS8-33096, from the George C. Marshall Space
Flight Center, Alabama. The NASA Technical officer
for this contract is Mr. Robert E. Jones, Electronics
and Controls Laboratory.	 j
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LOGIC SYNTHESIS FROM DDL DESCRIPTION
	
'i
The implementation of DDLT%N and DDLSIM programs on SZL-32 Computer 	 j
System is now complete. These programs were tested with DDL descriptions 	
C
of various complexity. Testing with newer system descriptions will
continue.
An algorithm to synthesize the combinational logic using the cells
available in the sL'andard IC cell library was formulated. This algorithm
is now being implemented as a FORTRAN program. A description of the
algorithm is given in the Appendix.
Some corrections were made to the MINICOMPUTER description (Example 5)
in the First Annual Technical Report. An updated version of the description
and the corresponding simulation results are shown in Figure 1.
The future work inciudes the completion of logic synthesis algorithm
implementation, extension of the algorithm to include the synthesis of
memory elements, registers and the register-transfer equations.
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APPENDIX
COMBIMTIONAL LOGIC SYNTHESIS rROM
AN HDI, DESCRIPTION*;
Sajjan G, Shiva
Computer Science Department
The University of Alabr►ma in Huntsville
P.O. Box 1247
Huntsville, Alabama 35807(205) 895-6088
ABSTRACT
Hardware Description L.nguages are used to input
the details of a digital system into an automatic
design system, An algorithm to synthesize combinational
logic from the .description in one such language (DDL)
is discussed.
*Submitted to the 17th Design Automation Conference
Minneapolis, Minn. June 1980.
R1. INTRODUCTION
iiardwaoe Description Languages (IiDL) provide a convenient means of
:Uiputttng the digital system design details into a design automation
system. Although tiDLs were originally designed to be just description
media, they have been used in other functions such as simulation, fault
test generation, microcode generation, documentation, etc.. The use of
HDLs in LS1 design automation systems is not widespread because of the
difficulty in translating the HDL description into logic diagrams (or
connectivity lists or equivalent), non-familiarity of the hardware de-
4
signers with high-level language programming aspects, non-uniform design
}	 methodologies and the time and cost involved in transporting and tailor--
t
ing the HDL software developed at one design center to the other. How-
ever, the advent of VLSI forces that the design be thoroughly verified
at the earliest possible time in the design cycle to minimize the fabri-
cation costu brought about by the final changes in a design. Since a
suitable breadboard for a VLSI circuit is the VLSI circuit itself, a
thorough computer evaluation at the outset is mandatory. Figure 1 [1,2]
shows the complete schematic of-an IC design automation system. The
Computer Aided Design and Test System (CADAT) of the NASA Marshall Space
Flight Center [1] is organized as in Figure 1. Digital Systems Design
Language ('DDL) [3] has been selected [1] for the CADAT system. This
paper addresses the problem of hardware compilation from the DDL
description, i.e., the process of converting the output of the DDL
translator into logic diagrams (or connertivity list, net list, etc.).
2. DDL TRANSLATOR [3]
The DDL translator converts the DDL description of the digital
system into a facility table, a set of Boolean equations and a set of
I.
2
register transfer equations. Figure 2 shows an example description.
.,a Boolean equations generated by the translator are in Sum of Products
(SOP) form. The Boolean functions in the DDL description that were riot
in the SOP form are retained 4s they are by the translator. The de-
signer can thus generate all the Boolean equations in the SOP form only
if he desires. hence, the synthesis procedure: discusser] hare assumes a
SUP form for the Boolean functions.
3. THE STANDARD cnmi, lmmay
Table 1 shows a partial list of the standard cells available in the
CARAT system. Number of devices for each cell and the cell width (as a
measure of the silicon area needed) are a l.so shown. The last r_._► lumart
shows the literals in each product term of the fuor-ti.on realized by the
cell. Note that the patterns containing all is (11, 111, 1111) anu
those with one product term (1, 2, 3, G) correspond to a single gate
realization. Zt is desirable to realize a function by using larger
standard cells (if possible), as ahown by the implementations shown in
Figure 3 for an example Boolean function. The standard cell library
provides four cells that can realize a larger function than a gate
equivalent, i.e., 2222, 2112, 222, and 22. Also note that the maximum
number of inputs to a cell is 8 (2222). Hence, we limit the number of
literals in a Boolean function to be realized to 8. A function larger
than this needs to be redlined in several 8 literal units. For 'example,
Z- P+ Q	 where P and Q are 8-literal lin is
Ir	 r and Q are separately realized. A, NAND
cell is used to combine them to form Z
3i
4. THE SYNTIMSTS ALGORITHM
1) Scan the Booloanfunction to be implemented and count the number of
literals in each product term to generate the literals/product term
pattern for the function.
2) If the function pattern is that of a SUM term (patterns containing
onl ,  ls: 1, 11, 111, etc.):
	 implement using the NOR calls with
proper number of inputs followed by a NAND call; stop.
3) If the function pattern is that of 4 PRODUCT tarn (patterns 2, 3, 4,
etc.): implement using the NAND cells with proper number of inputs
followed by a NOR cell; stop.
4. Reduce the product terms with more than 2 lit(rals into a term with
1 literal	 Wie--e tarsus are kuplemented as in Step 3).
	
If' the
function pattern reduces to all ls go to Step 2, else proceed.
5. Scan the function pattern to identify the : ttandard patterns: 2222,
2211, 222 1, 22 in t1wit order.	 Eliminate the matching portion of the
function pat"Ierri if the patterns or partial patterns are found (A
partial pattern is one which matches the standard call pattern
everywhere except in one digit, for example:
2221 Is implemented as 2222
2111 is Implemented as 2211
21 is implemented as 22)
6)	 If the function pattern is exhausted, sLop- If not, go to Step 2,
Note that the algorithm does not minimize the Boolean function.
Only the literals are counted, not the actual number of input variables
needed. This might result in slightly higher cost implementations of
some functions when the same input variable repeats. For example:
N
54
A+BS+ODE
could be impleir.ented with two cells: 1880 and 1220. (14 devices, 20.7
mils). Ustag the algorithms
A+BE+OF
Stop 1)	 1 2
	
3
star, k)	 1 2
	
1
Step 5)
Step 2)	 0 2	 1 <---From Stop 5
The implementation needs three cells: 1870 and 3, 1220a assuming
that A is not available. The cost is (20 devices, 27 mils).
CONCLUSIONS
An algorithm for selec tag standard cells for implementing the
combinational logic is presented. The algori.tivii is ouitable for imple-
mentation as a computer progtam. The Complete synthesis algorithms for
the CADAT system are now being investigated. These. algorithms extend
the algorithm presented here to include the memory cells (flip-flops)
and corresponding register-transfers. But the algorithm presented here
is suitable for any LST design environment.
ACKNOWLEDGEMENTS
This work is supported by the NASA-Marshall Space Flight Center
under the contract NAS8-33096.
REFERENCES
[11 S. G. Shiva, "Use of DDL in an Automatic LST Design System,"
Prod ^ lnternati.onal S}nn. CIIDLs, Palo Alto, CA, October 1979,
pp. 28-32.
"Hardware Description Languages - A Tutorial," Pro_c. TFBF,
D(,c. 1979.
t
5(31 D. L. Dietmover and J. R. Dulay, "Register Transfer Languages and
Their Translation," in Digital $Xotems DasiSnAutomation: Languages,
Shitulation and Data Baca, M. A. Brauer (ad), Computer Sciences press)
Woodland Ilillo f CA  1975.
t
Table 1« CARAT Standard Call Library (Partial)
(Cell No. Typo Nu. ofDevices
("d 1. width
(milt)
Function I,1teralo/'ruduct
Term
1120 2 input	 A CiR 4 5 . 8 A I3 1,1
1130 3 input	 N lit 6 7.7 A + B + C 1,1,1
1140 4 input
	 NOR 8 9.6 A +i 'B+  C f= b I,I,I,1
1220 2 input	 NAND 4 5.8 '94 2
1230 3 input	 HAND 6 7.7 A-,B•C 3
1240 4 input
	
NAND 8 9.6 AA	 D 4
1310 Buffer Inverter 2 3.9 A 1
1620 2 input	 AND 6 5.8 7--i 2
1630 3 input	 AND 8 7.7 A#BBC 3
1640 4 input	 AND 10 9.6 A•B-C•D 4
1720 2 input
	
OR 6 5.8 A + B 10 1
17301 3 input	 OF. 8 7. 7 A + n + C l,l, l
1740 4 input	 OR 10 9.6 A + B + C + D 1,1,1,1
1800 4 x 2 input AND + 16 17.2 2,2,2,2(9B	 UP+tit)
4 x NOR
1840 3 x 2^ input AND + 10 11.6 C (AB ++ DE) *
2	 input 'NOR
1960 2 x 2 input AND + 12 13.7 AB+B+F+CD 2,101,2
4	 input NOR
1870 2 x 2 input AND + 8 9.6 (AB +CD) 2,2
2 inpu t NOR
1880 2 bit carry 10 14.9 (CDE) +BE+ D*
Anticipate
1890 3 x 2 input AND + 12 16.9 99 + CD + BF 2,2,2
3 input NOR
2310 2 input rXOR 8 7.8 A @ B 1,1
1.
* Special Functions
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	AB + CA + EC + G	 -	 Function to be implemented
2	 2	 2 1	 -	 Pattern
Implementation Cells Needed	 _No. of Devices Area (Mils)
1 2221	 2222 1800 16 17.2
1220 4 5.8
*Total Cost 20 23.0
2 L::K2	 E2 i
^22^	 ti 22-J 1870 $ 9.6
1870 8 9.6
1220 4 5.8
Total Cost 20 25.0
3 [j2 U U Li__^ 4 x 1220 16 23.2
1240 8 9.6
24 32.8Total Cost
* Least Cost Implementation


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