The mechanisms limiting performance in polycrystalline silicon was determined. The initial set of experiments in this task entails the fabrication of cells of various thicknesses for four different bulk resistivities between 0.1 and 10 omega-cm. The results for the first two lots are presented

Culik, J. S.

Wohlgemuth, J. H.

English

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https://ntrs.nasa.gov/search.jsp?R=19830025052 2020-03-21T02:56:47+00:00Z
JPL VD. 9950438
DRL No. 156	 DOE/JPL 955902-82/6
DRD No. SE-3	 Distribution Category-63
Item 86
(RASA-CR-172982) PROCESS RESEARCH ON	 U83-33323
PULYCRYSTALLINE SILICON MATERIAL (PROPS!!)
Quarterly Report, i Mar. - 30 Jun. 1982
(So:arez Corp., Rockville, Ad.) 20 p	 Unclas
HC A02/MP A01	 CSCL 10A G3/44 28566
PROCESS RESEARCH ON POLYCRYSTALLINE SILICON MATERIAL
(PROPSM)
QUARTERLY REPORT NO. 6
MARCH 1, 1982 - JUNE 30, 1982
	
otc^^
CONTRACT NO. 955902
9%1
'ARFX'7%% on
DRL No. 156	 DOE/JPL 955902-82/6
DRD No. SE-3
	
Distribution Category-63
Item #6
PROCESS RESEARCH ON POLYCRYSTALLINE SILICON MATERIAL
(PROPSM)
QUARTERLY REPORT NO. 6
MARCH 1, 1982 - JUNE 30, 1982
CONTRACT NO. 955902
The JPL Flat-Plate Solar Array Project is sponsored by the U.S.
Department of Energy and forma mart of the Solar Photovoltaic
Conversion Program to initial a major effort toward the
development of low-cost solar arrays. This work was performed
for the Jet Propulsion Laboratory, California Institute of
Technology by agreement between NASA and DOE.
BY
JOHN H. WOHLGiEMUTH
JERRY CULIK
SOLAREX CORPORATION
1335 Piccard Drive
Rockville, MD 20850
(301) 9119-020"1
1.0 INTRODUCTION
i
I
I
2.0 TECHNICAL PROGRESS 	 2
2.1 Documentation	 2
2.2 Revised Program Plan	 2
2.3 Fabrication of Cells of Various Thicknesses	 6
3.0 SCHEDULE AND PLANS	 10
REFERENCES	 17
I
1
t 1
t
I
1.0 INTRODUCTION
The emphasis of this program has been changed from the
design, development, and fabrication of an automated production
process to the investigation of polycrystalline silicon to
determine the mechanisms affecting conversion efficiency and to
the development of processes that take full advantage of its
potential as a photovoltaic material. In light of this change
of emphasis the name of the program has been changed from Module
Experimental Process Development Unit (MEPSDU) to Process
Research of Polycrystalline Silicon Material (PROPSM).
During this quarter a revised program plan was prepared
describing the program effort for the PROPSM contract. A
description of the technical program plan appears in Section
2.2. The first task is to determine the mechanisms limiting
performance in polycrystalline silicon. The initial set of
experiments in this task entails the fabrication of cells of
various thicknesses for four different bulk resistivities
between 0.1 and 10 D-cm. The results for the first two lots are
presented in Section 2.3.
2.0 TECHNICAL PROGRESS
2.1 Documentation
The following reports were submitted during this quarters
26 Technical Progress Report No. 16
27 Quarterly Report No. 5
28 Program Plan for PROPSM
29 Technical Progress Report No. 17
30 Technical Progress Report No. 18
31 Technical Progress Report No. 19
2.2 Revised Program Plan
The emphasis of the program is now on the investigation of
polycrystalline silicon to determine the mechanisms affecting
conversion efficiency and on developing processes that take full
advantage of its potential as a photovoltaic material. The
initial effort under Task #1 will be to determine the Mechanisms
Limiting Performance in polycrystalline material. Task #2
efforts will thus be the Development of Processes to Improve
Performance of polycrystalline Lolar cells. The efforts to be
performed are described in the following sections.
2
I U
MR
TASK 1 - Mechanisms Limiting Performance
EXPERIMENT 1 - Bulk Resistivity Experiments
Cells will be fabricated using a minimum of four different
bulk resistivity values in the range 0.1 to 10 O-cm. For each
bulk resistivity, wafers of thickness 300, 250, 200, 150, 100,
50 microns will be processed into solar cells using a well known
high efficiency cell process with a back surface field (BSF).
The results of short-circuit current as a function of bulk
resistivity should provide a measure of the effective minority
carrier diffusion length as compared to that of single crystal
silicon. The dependence of open-circuit voltage on wafer
thickness will also provide information on the minority carrier
diffusion length for the various bulk resistivities. The
dependence of open-circuit voltage on bulk resistivity will help
to identify the voltage limiting mechanisms as compared to
single crystal silicon where the voltage limiting mechanism
shifts from the bulk to the emitter as the bulk resistivity
drops from 10 n -cm to 0.111-cm. Comparison of polycrystalline
material results with single crystal results should indicate
whether the bulk is controlling the open-circuit voltage or
whether grain boundary effects dominate.
3
f
f
EXPERIMENT 2 - Silicon Substrate Experiments
A variety of 10cm x 10cm polycrystalline wafers will be
processed into samples containing 400 isolated 0.5cm x 0.5cm
mini-cells. Electrical performance of each of the mini-cells
will be measured. Contour plots of I sc , Voc • Pmax and diode
factor will be made. In regions of interest (such as very high
or low performance) localized Voc probing or spot scanning of
Isc will be conducted. Attempts will be made to equate
performance to macroscopic structure (i.e., placement in the
brick) and microscopic structure (i.e., grain boundaries, twins,
etc.). Attempts will be made to understand the functional
dependence of I sc , Voc, and diode factor on the various
structures.
Interpretation of the results of these two experiments will
aid in determining the mechanisms limiting cell performance.
This will be used to update the theories of polycrystalline cell
performance and to select for further investigation those
process techniques or process modifications which may lead to
the most significant improvements in cell performance.
TASK 2 - Processes To Improve Performance
The measurements and analysis in Task 1 will determine the
types of process developments most likely to aid cel;.
4
efficiencies. Process areas to be investigated may include, but
not be limited to, the following:
1. Hydrogen Passivation of Grain Boundaries - A number of
studies have been conducted in the area of hydrogen
passivation of grain boundaries. The use of hydrogen to
take up dangling bonds is a proven technology, especially
for a-Si. The value of this method for a large grain
polycrystalline silicon remains to be shown.
2. Enhanced Diffusion Down Grain Boundaries - Light diffusion
down grain boundaries enhances current collection near the
boundary. The use of selective etching including plasma
etching can lead to enhancing the diffusion paths down the
grains. It may then be possible to get increased
performance near the grain boundary, at least for shorter
wavelength light.
3.	 Gettering	 - Gettering	 has	 been	 shown	 to	 improve cell
performance when	 there	 are	 impurities	 present.
	
The	 first
step	 would be	 to	 determine	 if	 gettering	 improves cell
performance and,	 if	 it	 does,	 to	 determine	 whether the
improvement is	 due	 to	 changes	 in	 the grain bulk or	 at the
grain boundaries.
t[	 5
tt
e
t
4. Surface Passivation - The irregularity of polycrystalline
silicon surface compared to that of single crystal silicon,
may result i: ► higher surface recombination velocities and
lower open-circuit voltages. If this hypothesis is
confirmed during Task 1, the efforts to passivate the front
surface, such as growth of a thin oxide or deposition of a
thin window layer of higher band gap material like w.-Si
or a -SiC, may significantly improve cell open-circuit
voltage.
The results of these process developments will be analysed
to include the effects on cell efficiency, process cost,
compatibility with other cell processes, and the applicability
of the process to particular polycrystalline materials.
2.3 Fabrication of Cells of Var!Lus Thicknesses
The process sequence for the solar cells is shown in Figure
1 and is described in detail in Reference 1. This is a standard
BSF space-cell process that produces high efficiency cells on
all single crystal thicknesses. (It did not ivclade texturing,
double layer antireflective coating (AR) or back surface
reflection, which are required to produce maximum efficiency
from 2 mil cells.) The cells are 2cm x 2cm in size with space
type Ti/Pd/Ag metallization and Ta205 single layer AR coating.
6
In each experiment a particular bulk resistivity is
selected. Polycrystalline wafers (usually supplied by Semix)
are coprocessed with single crystal wafers of similar bulk
resistivity. A CP-type etch (a mixture of HF-acetic-nitric
acids) is utilized to thin the wafers to various thicknesses
between 50 and 300 microns. After processing, the cells are
measured at AMO, 135.3 mW/cm2 and 250C. In addition the
spectral response of the short-circuit current is compared by
measuring the "red" current using a #2408 Corning filter and by
measuring the "blue" current using a #9788 Corning filter.
The first two lots were completed during this quarter. Lot
#1 was fabricated using 1 a-zm silicon, while Lot #2 used 3 O-cm
silicon. The results are summarized in Tables #1-5. The
averages in these tables do not include cells from the following
two categories.
1.	 Severe shunting is prevalent on many of the thinner cells
both single and polycrystalline. This may to due to
penetration of the aluminum paste through the entire
wafer. High yields of thin cells with this process require
more care with paste application and firing profiles. The
use of polycrystalline silicon does not appear to affect
the incidence of the shunting.
7
ut
t
t
t
t
2. A number of polycrystalline cells in Lot it had low current
and voltage, but with good fill factors. Such curves have
been seen in the past in material with de,7raded
minority-carrier lifetime (see, for example Reference 2).
It is likely that some wafers or parts cf wafers in this
lot had unusually low minority-carrier lifetime.
The results of the single crystal controls for Lots #1 and
#2 were similar, with all parameters improving with increasing
thickness, because a thicker cell absorbs more light in the bulk
and produces more electron-hole pairs. The reduced open-circuit
voltage for thinner ells indicates that the BSF may not be the
dominant mechanism controlling the voltage for these bulk
reststivities. Lot #2 controls had appreciably better
performance than Lot i'1 controls, i.e., peak power of 75-76 mW
versus 73 mW for 250 micron thickness cells. This improvement
was entirely due to higher open-circuit vol l-age, i.e., 605-607
W versus 597 mV at 250 microns. This of course is not
consistent with the expected dependence on bulk resistivity;
that is, higher bulk resistivity yields lower cell open-circuit
voltage which could be due to a combination of higher
minority-carrier lifetime (allowing more influence of the BSF)
for the 30-cm  silicon, or it could be the result of improved
processing (although the process parameters for the two lots
were supposedly identical).
1	 8
cThe polycrystalline cells do not show improvement of all
parameters with increasing thickness. Indeed the highest
open-circuit voltage was obtaine+ for the thinnest cells,
indicating that for this polycrystalline silicon the HSF ray be
able to significantly enhance the voltage. While the dependence
of short-circuit current and red current is different in the two
lots, the ratio of polycrystalline to single-crystal short
circuit current and red current is the highest for the thinnest
cells in both lots. This is an indication that the first 50 or
100 microns of the polycrystalline material is reasonably
efficient at current collection. However, collection of
carriers deeper than 100 microns is not nearly as efficient for
the polycrystalline cells as for the single-crystal solar cells.
The blue current shows little dependence on thickness, bulk
resistivity or cryat^l structure. As expected, it is more a
function of the process sequence.
t
t
I
9
3.0 SCHEDULE AND PLANS
During the next quarter the set of experiments to fabricate
polycrystalline cells of various thicknesses will continue,
including one lot with higher bulk resistivity, approximately
8 n -cm, and another with lower bulk resistivity, approximately
0.3-0.6 P-cm.	 Efforts will begin to prepare for the silicon
substrate experiments with 400 mini-cells c r i one wafer.	 In
addition, efforts will continue on the MEPSDU Summary Report.
10
ORIG NAL PAGE tS
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CELL PROCESS SEQUENCE
wpwis
OF P" qumjvy
CP THINNING
ETCH
CUT EDGES
GASEOUS
DIFFUSION
Al PASTE
BST'
PHOTJLITHOGRAPHY
EVAPORATE Ti-Pd
FRONT AND BACK
Ag PLATE
Ta205
EVAPORATED AR
TO SIZECUT
FIGURE 1
15
REFERENCES
1. G. Storti, J. Culik and C. Wrigley, "Development of a High
Efficiency Thin Silicon Solar Cell", Final Report, JPL
Contract No. 954883, December 1980.
2. J. H. Wohlgemuth and M. N. Giuliano, "Analysis of the
Effects of Impurities in Silicon", Final Report, JPL
Contract No. 955307, January 1980.
17


Process Research On Polycrystalline Silicon Material (PROPSM)

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