A circuit is described to produce arbitrary time-dependent voltage functions derived from digital information stored in EPROMs. While this circuit is designed to be used as a modulator of the microwave pump source or a solid state low noise maser, it can be readily adapted for other applications

Fowler, L.

Mcneil, J. A.

English

NASA Technical Reports Server

TOA Progress R~port 42-75 
An EPROM-Based Function Generator 
L. Fowler and J. A. McNeil 
Radio Frequency and Microwave Subsystems Section 
A circuit is described to produce arbitmy timedependent voltage finctions derived 
fiom digital information stored in EPROMs. While this circuit is designed to be used as a 
modulntor of the microwave pump source for a solid state low noise maser, it can be rad -  
ily udapta ]or other applications 
1. Introduction 
Although there are many published descriptions of circuits 
to generate specific (sinusoidal, logarithmic, etc.) or arbitrary 
waveforms using electrically programmable read-only memory 
(EPROM) and digital-to-analog co,nerter (DAC) devices, this 
report presents an implemeirtation that is somewhat unique in 
that (1) it can be controlled and monitored externally by a 
computer through parallel ports, and (2) it can be programmed 
to hold a particular output, or to  sweep over any portion of 
the output function without sweeping the er,tire iange. These 
special features make this circuit particularly useful as a volt- 
age source for the frequency mGdulation of an IMPATT oscil- 
lator, which is used as a microwave pump for the solid state 
masers used in the DSN as very low noise amplifiers. Since the 
waver ’ is determined by the operating characteristics of an 
indi. $4 maser, the use of an EPROM allows the waveform 
to be readily modified. The discussion of this particular appli- 
cation will be the subject, however, of another TDA report. In 
this report we describe the circuit and its operation. 
II. Circuit Design and Description 
The circuit described here provides a periodic voltage of 
amplitude corn 0 to 10 volts, with 12-bit resolution, tiiilizing 
reaa 1y available components. In addition to  the two :equire- 
ments described above, this circuit is designed to provide an 
output symmetrical about one-half the total period. 
Figure 1 shows a block diagram of the circuit. The symmet- 
rical output is achieved by controlling a 12 bit up/down counter 
to count up continuously from a low \ d u e  (low limit) to a high 
value (high limit) and then reversing direction (Le.? count down) 
until the low limit is reached ab-in. This linear digital sweep 
produced by the counter isused a i  the address for the EPROM, 
whose output is then tied to the DAC where the output volt- 
age is produced. (The output can be held constant by setting 
the high limit and the low limit equal to each other.) 
Figure 2 shows the schematic for the clock oscillator, the 
low and high limit comparators and logic providing the up/ 
down control, and trr, Lommand decoder prviding the ex- 
ternal control. A brief description of each sectioa is F::cented 
here. 
A. Clock 
The clock signal is generated by a (74C14) Schmitt trigger 
oscillator and is buffered by another Schmitt trigger. This sig- 
nal is steered by the counter control logic to  provide the count 
up snd count dowll clocks for the binary counter. The clock 
frequency used in this application is 2 MHz, which at 32 point/ 
period provides an output frequency of 60 kHz(2000 kHz/32). 
6. Counter Control Logic 
High and low limits supplied by the data bus are stored by 
h:x latches (7x174)  when enabled by the command decoder, 
79 
https://ntrs.nasa.gov/search.jsp?R=19840005340 2020-03-21T01:50:23+00:00Z
and compared to the EPROhS address as provided on the 
counter bus. Cascaded 12-bir magnitude comparators (74(385) 
provide low/high limit signals to the upldown counter con- 
troller circuit, which when enabled on the positive clock tran- 
sition drive the bidirectional binary counter. The lcgic insures 
that the munters start 3t known value and begin sweoping in 
the proper direction. 
C. Command Decoder Circuit 
Commands provided on the control bus are decoded by 
Intel (8205) 3 bit to  8 line decoders to provide four commands. 
U24 prcjvides a card type select decoder, U23 a unit select, and 
U22 provides a cornmand select. As implemented here, the 
command syntax is as follows. 
b i t 7 6 5 4 3 2 1 0  
0 0 1  o o o x x  
x x x . . . . . c a r d t y p e , O J  
x x x . . unit number,O-7 
0 0 run 
0 1 load low limit. hold 
1 0 load high limit, hold 
1 1 load low and high limit, hold 
This syntax was chosen so that the command byte can be gen- 
erated in software by OXing with masks. 
Figure 3 shows the schematics for the binary counters, the 
EPROMs, the DAC, and output stages, which we describe here 
briefly. 
0. Binary Counter 
Th: binary up,’down counter consists of three 4-bit preset- 
table up/down counters (74C193) cascaded with the clear in- 
puts disabled. A load high and low command causes the twelve 
bits on the data bus to  be loaded simuitsneoudy into the high 
and low comparators an& the binary counters. The quality sig- 
nals from both comparators prevent the clock signal from ap- 
pearing at the count up or down clocks. Thus the address on 
the EPROM is a fixed value, and the output of the DAC will 
be held at the corresponding fixed voitage. In this manner the 
function can be swept through point by point by the external 
computer. If, however, the load high and low command is fol- 
lowed by a load low (or high) command. the binary counter 
and the low (or hifh) ;omparator are loaded with new data to  
he fLund on the data bus. Only one of the low (or high) com- 
parators now shows equality, and the steering logic will cause 
the counters to ramp up (or down) starting at the low (or high) 
address entered. (There is nothing to pr’vent low value to 
exceed the high value. The counter will increase from the low 
value entered, wrap around the zero, and continu- to  increase 
untii the high value is reach. 1, then reverse its direction.) 
Since the EPROMs used here are Intel 2716 (2048 x 8). only 
the eleven counter bits 0 to io are used to  provide the address- 
ing. However, all twelve bits are used by the control logic. 
E. EPROM 
Two EPROMs are addressed in parallel to provide 16-bits of 
output data. Since the DAC chcsen is a 12-bit converter, four 
of the data lines of the second EPROM are not used. 
F. DAC and Output Stage 
The DAC used here is the Analog Devices HDD1206SM, 
which has an integral sample and hold circuit to minimize the 
effects of switching transients, and is sufficiently fast to pro- 
vide satisfactory operation at 2 MHz. Uniform switching 
transients are observed, and are measured to  be less than 
3 x 2-12 of the output with settling times less than 100 ns. 
Two op amps provide level shifting and buffering at the out- 
put, and two potentiometers allow for adjustments of offset 
and gain for 0 to !O volt output. 
HI. Comments 
The clock frequency is determined by the choice of R1 and 
C1. The command of the circuit at the bus can be modified at 
U22-U24. Alternate!!. the circuit can be hardware controlled 
by connecting the lines at U22, pins 1, 2, and 3 to a rotary 
switch. Straightforward modifications to the steering logic pro- 
viding the load counter, count up clock, and count down clock 
will allow this circuit to  sawtooth in either direction. In order 
to use 2732 EPROMs, the bit 11 output from the binary counter 
would be used to address the EPROMs. The overall perform- 
ance of this function generator is dominated by that of the 
DAC. Adaptation of this circuit to more demanding specifica- 
tions may dictate the use of a higher performance DAC. U21 
is used here only as an active pull up for U6. U11, U14, U23, 
and U24, and four of the hex inverters in U30 are unused. 
The capacitors CS through C26 denote by-pass capacitors for 
each IC. 
ao 
O~~IGINAL PAGE rs 
OF POOR QUALITY 
- UPDOWN - ~ 
COUNTER CLOCK EPROM - DAC 
Fig. 1. The block diw 
causing the upldown 
counter provides the 
analog signal by tht 
t 
INTERFACE - CONTROL 
-control logic, which is derived from a OOmmandon the bus, 
veep between two limits, also derhred from the burr Tho 
b EPROM, the output of which is convertad to the desired 
*dl stage pmvider scaling and buttering. 
t 
OUTPUT ' 
81 
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83 


An EPROM-based function generator

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