The present conception of the data processing scheme is described including the Main Processing Units (MPU) and Satellite Processing Units (SPU) which will acquire the data for the instruments presently planned in the International Solar Terrestrial Physics (ISTP) Project

Torbert, R. B.

English

NASA Technical Reports Server

. 
INTERNATIONAL SOLAR-TE RRESTRIAL PROGRAM 
DATA PROCESSING CONSORTIUM 
Purchase Order No. H-78750B 
Final Report 
UAH Research Report No. 530 
\ 
( N A S  A-CR- 17 89 19 ) 
S G L A R - T E R R E S T B 1 A . I  EROGBRIYI OAlA EGCCESSING 
INT EE N AT ICW AL N87-11676 
C C N S C E T I U M  Pirtal Report [Alatama LrniY,, 
H u n t s v i l l e . )  11  F CSCL 03U U n  c 1 a s 
G3/92 43759  
BY 
Roy B .  Torbert, Ph.D. 
Principal  Investigator 
School of Sciences 
Physics Department 
Prepared For 
National Aeronautics and Space Administration 
George C .  Marshall Space Fl ight  Center 
Marshall Space Fl ight  Center, Alabama 35812 
September 3 ,  1986 
https://ntrs.nasa.gov/search.jsp?R=19870002243 2020-03-20T14:01:36+00:00Z
Final Re’port on 
International Solar-Terrestrial Program 
Data Processing Consortium : 
Purchase Order # H-78750B 
Introduction. 
The University of Alabama in Huntsville ( UAH ) effort 
for the common design of a Data Proccessing Unit (DPU) for use on 
the ‘International Solar Terrestrial Physics Program (ISTP) began 
sometime in December 1985 with meetings at Goddard Space Flight 
Center among all the principals including University of Alabama in 
Huntsville, University of California, San Diego, University of 
California, Berkley, University of Washington, and Goddard Space 
Flight Center. This meeting defined the requirements that such a 
system should have to accomodate the needs of five instruments in 
the ISTP program . Appendix 1 combines together these requirements 
that at this time, we feel the instruments can accomodate. 
Briefly, the initial design effort covered under this purchase 
order has allowed us to: 1) investigate the 32016 Prototype board 
with the %iny development system; 2) acquire the P-CAD development 
system which allows for automated circuit drawing and circuit board 
layout, 3) to put down our initial design of the processing unit 
Mother Data Processing Unit; 4 )  to begin to establish coordination 
among all members of the DPU Consortium that can be accomodated 
over the SPAN network (Space Physics Analysis Network). Most 
elements of the DPU Consortium now can be addressed on the SPAN 
network in a routine manner. Appendix 2 gives their SPAN network 
addresses. 
In the interval since this effort began, several new facts 
have changed the direction of the DPU design. Most importantly, is 
the fact that the entire ISTP program now looks as if it may be 
delayed by up to two years. This consideration and the established 
schedule for the 32016 design at Sandia Laboratories implies that 
tne entire proccessing scneme wiii be based totaiiy ui-oiiiid 32Ci8 
processors. Secondly, we now have acquired an operating FORTH 
language operating system for the 32016 base microproccessor 
systems with targeted cost compiler. This UNIFORTH system operates 
and allows one to develop microprocessor code on an IBM PC, 
cross-compile to the 32016, and then execute code in the 32016. 
With this capability, we feel that the FORTH operating system is 
the best to pursue for language and operating systems. It is also 
probable that there will be a second source FORTH operating system 
for the 32016 provided by LMI of California. 
MAIN PROCESSING UNIT 
In the following sections we describe our present conception 
of the data processing scheme including Main Processing Units 
(MPU) and Satellite Processing Units (SPU) which will acquire the 
data for the instruments presently planned in the ISTP Project. 
The MPU will be organized into 5 boards and a power supply. 
The five boards are as follows: 1) Processor Board, 2) Memory 
Board, 3) Peripheral Interface Board, 4 )  Spacecraft Interface 
Board, and 5) Accumulator Board., The SPU will be organized into 3 
boards ar,d a power supply. Three boards are as follows: 1) 
Processor Board, 2) Peripheral Interface Board, and 3) Accumulator 
Board. 
The MPU’s processor board will contain a 32C016 16-bit 
microprocessor with associated Timing Control Unit and Floating 
Point Processor. This three chip set computer will provide the 
processing power required for the in-flight data reduction. The 
board will contain a minimum of ROM and RAM to execute the FORTH 
kernel and application software. Circuitry will be included to 
interface with the rest of the system as well as an RS-232 
link for ground testing. A watchdog timer is required to reset 
the system if a single point radiation failure interrupts 
processing. 
- 
The MPU’s memory board will contain a 256k-byte mass memory 
for burst data storage. This memory will utilize 32 64k-bit 
chips and associated decoding logic. The processor board will 
reduce this large amount of data to meet the telemetry constaints 
of the down link. The MPU’s peripheral interface board will 
provide the necessary interfaces to the SPU and the High Voltage 
Supplies in the system. The SPU interfacg will be a Marxhester 
encoded bi-directional data link for command initiation and data 
recovery. The HV supply interface will be a three wire data 
transmission scheme utilizing a data path, a gated clock and an 
data enable. 
The MPU’s spacecraft interface board will provide the 
necessary interface to the satellite for data transmission to the 
ground, and data reception of satellite position and ground 
commands. Since this interface has not been determined, a full 
card slot has been dedicated for use. 
The MPU’s accumulator board provides the data recovery from 
the particle detectors in the system. The board will comprise 
82C54 counter/timers which contain three 16-bit accumulator 
c’iiiliitieis. Associated circuitry wiii control the accumuiation 
interval and enable data to the 
The SPU will use the same boards as the MPU except some part 
will be removed. The SPU’s processor will not require the memory 
interface and high level of subsystem decoding as required in the 
MPU. The rest of the SPU is anticitated to be identical to the 
MPU . 
Software 
The system software f o r  the 32C016 processor boards will use 
the FORTH programming language. The software will be written on 
an IBM compatible computer and can down loaded to the MPU or SPU 
RAM for testing before the final code is cross-compiler to ROM 
for flight. FORTH was chosen because of its ease of programming 
and debug, personnel experience, and its close control of 
processor functions. Since the units provide a terminal ground 
link, test code can be downloaded during ground testing 
and deleted for flight for optimum use of processor memory. 
Present and Future Work 
The MPU will be modeled after telemetry units in use on 
sounding rocket programs. The new processor board is in the could 
be built and tested in a following design phase and a wire-wrapped 
prototype could be built. A similar design board utilizing the 
32C016 processor will be built and flight tested on a sounding 
rocket in 1QFY87. Design of the spacecraft interface board is 
awaiting definition of the interface or design of the spacecraft 
subsystem. 
M A I N  
P ROCESS ING u NIT 
I 
RS-232 
L\N K 
I 
SPACE C R B l T  
INTERFACE 
G R O U N D  
SUPPORT 
EQ Lll PMENT . 
I MEMORY 
I PERIPHERAi INT€RFACE 
L .- . . . . . . I _  . . .  I -  
. *. .-____ .I - I - .  . - 
Appendix 1 : Requirements f o r  
Common DPU’s 
Design vs F a b r i c a t i o n  Phases 
Design w i l l  be  sha red  amongst UCB, UCSD, and UAH. .  F a b r i c a t i o n  
w i l l  take p l a c e  a t  UCSD, l ayou t  a t  UCB.. 
Budgetary Management Guide1 ines 
Note, i n  t h e  fo l lowing  matrix, t h a t  money can f l o w  a long  
vertical  l i n e s  wi thout  such p e n a l t i e s  as double  overhead charges,  
e tc . ,  and t h a t  s t a r t u p  occurs  along h o r i z o n t a l  l i n e s .  ie:  Wind gets 
funded be fo re  P o l a r  and 
d o e s n ’ t  charge overhead 
branch of t h e  U C a l  can 
s u b c o n t r a c t i n g  it.. 
Wind 
Polar /Equator  
For t h e  des ign  phase it 
Equator . .  P a r t l y  t h i s  is because U Wash- 
on subcon t rac t s ,  and because a c o n t r a c t  a t  one 
pay c o s t s  i ncu r red  a t  ano the r  branch wi thout  
U C a l ,  U Wash GSFC 
Lin O g i l v i e  
Parks ,  McIlwain Scudder 
is up t o  each (ver t ical)  funding fami ly  t o  
ba l ance  t h e i r  c o s t s  i n t e r n a l l y ,  so t h a t  money does r o t  have t o  pass 
back and f o r t h  h o r i z o n t a l l y . .  T h e r e  is  one except ion  t o  t h i s  
s e p a r a t i o n ,  and t h a t  is t h a t  UCB w i l l  p rovide  t o  UCSD a 10 K$ budget 
t o  e n a b l e  UCSD t o  monitor t h e  i n i t i a l  de s ign  and par t ic ipate  as much as 
it c a n . .  
E i i r ing  t h e  fatricuiiori  phase, each p a r t i c i p a n t  w i i i  nave to 
break  t h e  budget he  p r e s e n t s  t o  t h e  p r o j e c t  i n t o  two parts: one t h a t  
he spends f o r  h i s  purposes  alone, and t h e  o t h e r  which is h i s  s h a r e  of 
t h e  t h e  common microprocessor  e f f o r t . .  Microprocessor f e a t u r e s  t h a t  
are n o t  par t  of t h e  common design must be provided and pa id  f o r  by t h e  
i n d i v i d u a l . .  If f a b r i c a t e d  a t  UCSD, t h e  i n d i v i d u a l  w i l l  be b i l l ed  
s e p a r a t e l y . .  
Management 
A t  t h e  s c i e n t i f i c  level, t h e  h i g h e s t  a u t h o r i t y  w i l l  be a 
c o u n c i l  of t h e  P I ’S  and Co-1’s.. For day t o  day t r a c k i n g  of d e t a i l s ,  
There w i l l  be a Manager f o r  t h e  design phase and ano the r  f o r  t h e  
f a b r i c a t i o n  phase . .  Dave Curkis w a s  nominated f o r  t h e  des ign  phase,  
and R o y  Torbe r t  f o r  t h e  f a b r i c a t i o n  phase . .  
Cornmimicat ions  
Use t h e  SPAN network, with CAD/CAM u t i l i t i e s . .  
Technical Features 
It was proposed that the main and peripheral processors have 
the same board sizes and backplane bus.. - It was suggested that the backplane bus should be based on the 
IBM PC or PC/AT bus or a subset thereof.. 
Intercommunications should be via serial lines with several 
priority lines.. 
The box that houses the microprocessor should not be included 
in the common design, as different experiments will use different 
numbers of boards.. However, the boxes are constrained by the choice 
of board size, and so the mechanical interface that the box has to 
meet will be called out.. 
Technical Requirements 
L 
i 
n 
0 
g 
i 
1 
i 
e 
V 
P 
a 
r 
k 
S 
u 
Y 
d 
r 
a 
Configuration 
Main 
Daughters 
Stepdaughters 
1 1 
? 2 
1 
2 
1 1 
1 1 
3 
Number of serial interfaces 
on main board 2 1 2 1 4 
Count accumulators (16 bit) 
Main 16 
Daughter 48 
Daughter 48 
16 0 
16 48 
48 
24 ? 
24 8 
D/A Controllers (HV/Discr.) 0 
Main 
Daughter 
4 0 
Digital Lines for Device Control 
Main 8 
Daughter 8 
Daughter 8 
4 8*n 
8 
8 
0 
8 
8 
>64 kbit external memory Y Y 
Y 
Y 
Y Y Y 
Y 
Y 
Spacecraft Interface Y Y Y 
Ground Support Equipment Y Y Y 
Spacecraft Simulator *Y ' Y 
RS232 Interface Y Y 
Power Converter Y Y 
power allocation 12 w ? 
Digital Timing Lines -2 81, 80 
Analog sampling 8x8bits - 
Memory, main processor 
error-corrected RAM 16K 16K 
ROM 32K 32K 
Memory, peripheral processor 
error-corrected RAM 8K 
ROM 8K 
The processor board includes 
CPU 
Clock oscillator 
Timing functions with 82C54 registers 
ECCRAM and ROM 
Reset 1 ine 
Watchdog timer 
RS232 
Digital control bits 
Serial interfaces 
Y Y Y 
Y Y Y 
Y Y Y 
10 w 8 W  13-15W 
-2 8 ? 
nx8bits nx8bits ? 
16K 16K 16K+8K 
16K 32K 32K 
8K 8K 
8K 8K 
Common Fabrica,*on Budget 
6 styles of boards.  
Layout 
1 pro to type ,  1 f l i g h t  u n i t  apiece.. 
4 e x p m t s  5 e x p m t s  
100 K$ 100 K$ 
Assembly ( 3  people x 3 y e a r s )  
Outside h e l p  f o r  peak loading 
PC board procurement 
P a r t s  
Q u a l i t y  Control Subcontract  
Supp 1 ies 
GSE boards 
Management 
( 0 . 2 5  man-year dur ing  l ayou t )  
(1  man-year dur ing  f a b )  
Average Cost per Share 
470 K$ 
100 K$ 
50 K$ 
800 K$ 
100 K$ 
80 K$ 
20 K$ 
110 K$ 
1830 K$ 
460 K$ 
580 K$ 
120 K$ 
65 K$ 
1000 K$ 
100 IC$ 
100 K$ 
25 K$ 
1 2 0  K$ 
2210 K$ 
440 I($ 
UCSD : 
IJAH : 
GSFC : 
UCB : 
UWASH : 
Appendix 2 : SPAN Addresses 
CASS: :CEM ( McIlwain ) 
CASS::Fillius 
0PTICS::TORBERT 
: :BODET 
: :SISK 
LEPVAX::UZJDS ( Scudder ) 
: : U S K W  ( Ogilvie ) 
STAR: : "DWC%SSL@BERKELEY. EDU" 
( still undefined ) 
( Dave Curtis ) 


International Solar-Terrestrial Program Data Processing Consortium

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server