Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology

Trapp, O. D.

English

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WAFER LEVEL RELIABILITY TESTING: N 8 7 I 2 7 2 0 9 
AN IDEA WHOSE TIME HAS COME 
0. D. Trapp 
Technology Associates  
Por to l a  Valley, CA 
Abstract .  Wafer l e v e l  r e l i a b i l i t y  t e s t i n g  has been nu r tu red  i n  t h e  DARPA suppor ted  
workshops, h e l d  each autumn s i n c e  1982, a t  t h e  S tanford  Sierra Lodge on F a l l e n  Leaf 
Lake, Lake Tahoe, CA. The seeds  p l an ted  i n  1982 have produced an  a c t i v e  crop of VLSI 
manufacturers apply ing  wafer  l e v e l  r e l i a b i l i t y  test  methods. Computer-Aided 
R e l i a b i l i t y  (CAR) i s  a new seed  being nurtured.  U s e r s  are now being awakened by t h e  
huge e c o n m i c  va lue  of t h e  wafer r e l i a b i l i t y  t e s t i n g  technology. 
P lan t ing  Seeds 
I n  t h e  l a te  1 9 7 0 ' ~ ~  NSA a t tempted t o  i n s t a l l  wafer l e v e l  r e l i a b i l i t y  t e s t i n g .  The I C  
manufacturers would not  accep t  t h i s  concept. The idea of s t r e s s i n g  t e s t  s t r u c t u r e s  
t o  o b t a i n  t h e i r  lognormal f a i l u r e  d i s t r i b u t i o n  w a s  repugnant t o  say  t h e  l e a s t .  Most 
s u p p l i e r s  advised  t h a t  they  would n o t  supply wafers i f  t hose  kinds of tests were t o  
be done! 
I n  t h e  e a r l y  1 9 8 0 ' ~ ~  Paul Losleben moved from NSA t o  DARPA and aga in  asked t h i s  
au tho r  t o  e s t a b l i s h  wafer l e v e l  r e l i a b i l i t y  t e s t i n g  f o r  s p e c i f i c  a p p l i c a t i o n  f o r  the  
MOSIS program. The microe lec t ronics  indus t ry  has a long h i s t o r y  of r e s i s t i n g  ideas 
fo rced  upon them. Therefore ,  t h i s  au thor  be l ieved  our i n d u s t r y  should be nur tured  i n  
1 the  value of performing wafer l e v e l  r e l i a b i l i t y  t e s t i n g .  
The t e c h n i c a l  leaders  of t h e  I C  i n d u s t r y  were i n v i t e d  t o  send  t h e i r  key manufacturing 
people  t o  t a l k  and th ink  about  t h e s e  ideas i n  a workshop, open by i n v i t a t i o n  only.  
Only U.S. companies were pe rmi t t ed  t o  a t tend .  S t an fo rd  Univers i ty  and- Univers i ty  of 
C a l i f o r n i a  (Berkeley 1 co-sponsored t h e  workshops. These u n i v e r s i t i e s  a l s o  con t r ib -  
uted graduate  s t u d e n t s  t o  work ( f o r  t r a v e l  expenses)  and p a r t i c i p a t e  i n  open, free 
d i scuss ion  wi th  our  i n d u s t r y  t e c h n i c a l  leaders .  
I n i t i a l  Resu l t s  
The f i r s t  workshop concluded t h a t  a l though t h i s  w a s  an i n t e r e s t i n g  idea, it would not  
work; it was j u s t  p l a i n  imprac t i ca l ;  who would th ink  of doing a probe t e s t  on t h e  
wafer f o r  100's  of hours ,  etc.  B u t  t h e r e  was a glimmer of hope; t h e r e  was  a s t r o n g  
agreement t h a t  the workshop should be h e l d  again.  
The seeds d i d  f a l l  i n t o  f e r t i l e  minds and ideas  s lowly became plans  of ac t ions .  Why? 
The t i m e  w a s  r i g h t  f o r  t h i s  idea .  With the inc reased  d r i v e  f o r  h ighe r  performance 
VLSI devices  , we w e r e  awakened t o  new r e l i a b i l i t y  l i m i t a t i o n s .  W e  w e r e  demanding 
performance approaching t h e  " R e l i a b i l i t y  Mater ia ls  L i m i t "  i l l u s t r a t e d  i n  Fig. 1. I n  
t h e  1960's and 1970's t h e r e  w a s  a wide "Margin of R e l i a b i l i t y  Assurance." Our de- 
s i g n s  and process ing  could be s loppy but  the devices  s t i l l  y i e lded  and were reliable.  
But i n  t h e  1980's and beyond, t h e  "Device Ru les  and Device Performance" w i l l  be 
pushing up a g a i n s t  t h e s e  materials l i m i t s .  
https://ntrs.nasa.gov/search.jsp?R=19870017776 2020-03-20T09:25:42+00:00Z
Our a t t e n t i o n  was focused of s c a l i n g  a lgor i thms e s s e n t i a l  f o r  our moves from MSI t o  
VLSI. The new f a i l u r e  mechanisms r e s t r i c t e d  and r equ i r ed  modi f ica t ions  t o  t h e s e  
a lgor i thms.  Murray Woods of I n t e l  f r equen t ly  j o l t e d  our minds about  t h e  problems of 
1 um device r e l i a b i l i t y .  
A t  the  end of the second workshop, t h e  ques t ion  w a s  n o t  t h a t  wafer level t e s t i n g  
could n o t  be done, but  where w a s  it economic t o  do such tes ts?  The seeds had 
germinated and the  concept w a s  h e a l t h y  and growing. 
New products  use advanced des ign  r u l e s  and new technologies .  This i s  t h e  i d e a l  p l ace  
t o  eva lua te  wafer l e v e l  r e l i a b i l i t y  t e s t i n g .  The r e s u l t s  w e r e  s t a g g e r i n g  (Fig.  2 ) .  
By applying r e l i a b i l i t y  t e s t i n g  on t h e  wafer, no t  on packaged devices ,  it is p o s s i b l e  
t o  r ap id ly  so lve  r e l i a b i l i t y  problems t h a t  are found t o  e x i s t  with t h e  des ign  r u l e s  
and t h e  processes.  A normal q u a l i f i c a t i o n ,  as s p e c i f i e d  i n  MIL M 38510 o r  MIL STD 
883, r equ i r e s  approximately 1 2  weeks t o  complete a f t e r  t h e  devices  have been produced 
and assembled. By t h i s  technique,  i n  t h e  1970's t h e  average process/product  develop- 
ment cyc le  t i m e  was 40 months. Today t h a t  has been shor t ened  t o  an  average of 
30 months, f o r  fa r  more complex devices  and processes .  
By t h e  end of t h e  f o u r t h  workshop i n  1985, it i s  clear t h a t  t h e s e  i d e a s  n o t  on ly  apply 
t o  process/product  development, bu t  are c r i t i c a l l y  and economically important  i n  high 
volume manufacturing. 
There are s t i l l  issues t o  be resolved.  Can these wafer l e v e l  r e l i a b i l i t y  tests be 
c o r r e l a t e d  t o  t r a d i t i o n a l  packaged r e l i a b i l i t y  tests? D o  both of t h e s e  tests co r re -  
l a t e  t o  f i e l d  r e l i a b i l i t y  i n  VLSI  devices? These ques t ions  must be addressed  f o r  
each f a i l u r e  mechanism. The da ta  r epor t ed  a t  t h e  1985 workshop show tha t  wafer l e v e l  
r e l i a b i l i t y  tests do c o r r e l a t e  t o  both packaged a c c e l e r a t e d  stress tests and t o  
l i m i t e d  f i e l d  data.  
With o r  Without Wafer Level R e l i a b i l i t y  Tes t ing  
This comparison is complex (Fig.  3 ) .  There are  many i s s u e s  t o  cons ider .  Each manu- 
f a c t u r e r  and each use r  must understand t h e  b e n e f i t s  and o b l i g a t i o n s  of wafer l e v e l  
r e l i a b i l i t y  t e s t i n g .  Figure 3 addresses  t h e  b e n e f i t s .  What are t h e  o b l i g a t i o n s ?  
Any new approach r equ i r e s  changes, new l ea rn ing ,  acceptance of new va lues ,  job  
r e s t r u c t u r i n g ,  e t c .  
I f  e i t h e r  device u s e r s  or  I C  manufacturers  va lue  inexpensive,  c o n t r o l l e d  manufactur- 
i ng ,  then they  w i l l  want t o  have wafer l e v e l  r e l i a b i l i t y  t e s t i n g  on t h e i r  p roducts  
(F ig .  4 ) .  For the  U.S. ,  t h i s  is KEY t o  our  S t r a t e g i c  World Leadership.  Today much 
is  w r i t t e n  about the f a c t  t h a t  very few memory devices  are made i n  t h e  U.S.A. Should 
t h e r e  be a na t iona l  emergency tha t  would separate us  from our  major sources  of memory 
devices ,  w e  would be a t  a g r e a t  disadvantage.  By a broad implementation of wafer 
level r e l i a b i l i t y  t e s t i n g  w e  can rega in  t h e  necessary  s t r a t e g i c  r o l e  as VLSI l e a d e r s .  
CAR 
A t  the  1984 workshop w e  coined a new acronym, CAR. This s t a n d s  f o r  Computer-Aided 
R e l i a b i l i t y .  A l l  i n d u s t r i e s  have seen  t h e  b e n e f i t s  of CAD and CAM. Today des igners  
can r ap id ly  c r e a t e  very i n t e r e s t i n g ,  u s e f u l  devices  with the CAD t o o l s .  But i n  the 
a r e a  of r e l i a b i l i t y ,  few of t h e  r e l i a b i l i t y  engineers  f u l l y  understand each of t h e  
f a i l u r e  mechanism and t h e i r  imp l i ca t ions  t o  t h e  wide v a r i e t y  of VLSI designs.  How 
60 
t h e n  can w e  e d u c a t e  t h e  m u l t i t u d e  of des igners  s o  t h a t  t h e y  w i l l  n o t  create monstrous 
r e l i a b i l i t y  problems i n  f u t u r e  devices?  
The only  p o s s i b l e  way t o  a v o i d  f u t u r e  device chaos is  t o  p r o v i d e  a CAR too l  which can  
be i n t e g r a t e d  wi th  CAD. This i s  n o t  easy.  Most of our  f a i l u r e  mechanism mathemati- 
ca l  models are crude  a t  best. Most are t e s t e d  by h o l d i n g  a l l  v a r i a b l e s  c o n s t a n t  ex- 
cept one. U n f o r t u n a t e l y ,  devices  have many parameters v a r y i n g  a t  the same t i m e .  CAR 
w i l l  cost money. But t h e  v a l u e  r e c e i v e d  w i l l  be even g r e a t e r  t h a n  the v a l u e  of CAD. 
will t h e  U.S. accept t h e  c h a l l e n g e  or w i l l  it have t o  l e a r n  from o t h e r  n a t i o n s ?  Some 
a c t i v i t y  is beginning ,  u s i n g  i n t e r n a l  funds,  because our  VLSI manufac turers  know t h a t  
t he  r e t u r n  j u s t i f i e s  t h e  inves tment .  The workshop w i l l  c o n t i n u e  t o  n u r t u r e  t h i s  
idea. 
I 986 Workshop 
What is  h o l d i n g  back t h e  U.S. ae rospace  e l e c t r o n i c s  i n d u s t r y ?  That  is c l e a r l y  a 
q u e s t i o n  f o r  many t o  ponder.  W e  encouraged a e r o s p a c e  users and manufacturers  t o  par- 
t i c i p a t e  a c t i v e l y  i n  t h e  1986 Wafer R e l i a b i l i t y  Assessment Workshop. 
o n l y  a few have a t t e n d e d .  Does a meet ing have t o  be v i s i b l y  sponsored  by a c o n t r a c t -  
i n g  agency t o  a t t r a c t  a t t e n t i o n ?  C l e a r l y  t h a t  is impor tan t ,  b u t  advances can a lso 
o c c u r  o u t s i d e  of funded meetings and funded a c t i v i t i e s !  
I n  t h e  past  
The Wafer R e l i a b i l i t y  Workshops break  t h e  form of t h e  t r a d i t i o n a l  meetings.  
t h e y  have h e l p e d  n u r t u r e  a clear advance i n  r e l i a b i l i t y  c o n t r o l  and process c o n t r o l  
technology of doing a c c e l e r a t e d  l i f e  t e s t i n g  on t h e  wafer.  They are on the l e a d i n g  
edge of t h e  concept  of CAR. 
C l e a r l y  
61 
Margin of Reliability 
Assurance 
1960 1970 1980 1990 2000 
Figure  1 
Process/Product 
Development 
Cycle Time 
Trial h Error '1 I Before Qualification Tests Defined 
3 2l 1 Wafer Level Reliability Testing CAR = Computer-Aided Reliability 42 Months ? ? ?  30 Months 22 Months 1 15 Months m 
60s 70s 1986 90's 2000 
Figure 2 
62 
Wafer Level 
Reliability Testing 
Without With 
9 Qual Test - 12 Weeks Q Qual Test - On the wafer 
200 Devices - hours/days 
Q Very Slow Corrective 
Action - Years 
Q Not Competitive 
Slow Development 
Q Delays & 
Cost Overruns 
Q Adverse Reliability 
Surprises 
4b Cost - Expensive 
+ Yields - Variable or 
zero 
+ Who Does It? 
MIL STD Users 
Q Fast Turn-Around 
Corrective Action - Weeks 
Q 30 months for 80386. etc. 
4b Key to “Just in Time” 
Manufacturing 
Manufacturing - No Surprises 
4b Controlled Device 
Q Cost - Inexpensive 
+ Yields - High 
9 Who Does It? 
Commerical VLSI Makers & 
Computer Industry 
F i g u r e  3 
What  is holding back the 
U.S. Aerospace 
Electronics 
Industry? 
Figure 4 
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Wafer level reliability testing: An idea whose time has come

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