A power supply conditioning circuit that can reduce Periodic and Random Deviations (PARD) on the output voltages of dc power supplies to -150 dBV from dc to several KHz with no measurable periodic deviations is described. The PARD for a typical commercial low noise power supply is -74 dBV for frequencies above 20 Hz and is often much worse at frequencies below 20 Hz. The power supply conditioning circuit described here relies on the large differences in the dynamic impedances of a constant current diode and a zener diode to establish a dc voltage with low PARD. Power supplies with low PARD are especially important in circuitry involving ultrastable frequencies for the Deep Space Network

Loveland, R.

Primas, L. E.

English

NASA Technical Reports Server

N87:28776
_rogress Report42-90 April-June1987
ORIGINAL PAGE IS
0_. POOR QUALITY
Power Supply Conditioning Circuit
L. E. Primas and R. Loveland
Communications Systems Research Section
This article describes a power supply conditioning circuit that can reduce Periodic
And Random Deviations (PARD) on the output voltages of DC power supplies to -150
dBV (32 nanovolts/xffffz) from DC to several KHz with no measurable periodic deviations.
The PARD for a typical commercial low noise power supply is -74 dBV (200 microvolts/
x/rffz) for frequencies above 20 Hz and is often much worse at frequencies below 20 Hz.
The power supply conditioning circuit described in this article relies on the large differ-
ences in the dynamic impedances of a constant current diode and a zener diode to estab-
lish a DC voltage with low PARD. Power supplies with low PARD are especially impor-
tant in circuitry involving ultrastable frequencies for the DSN.
,Introduction
Often DC power supplies are characterized by the PARD on
,qr output voltages. The PARD is the periodic and random
viation of a DC voltage or current from its average value,
per a specified bandwidth, with all influence and control
tantities maintained constant. A bandwidth commonly used
!specify PARD is 20 Hz to 20 MHz.
r The PARD on the output voltage of a power supply used to
)wer RF circuitry results in undesired amplitude and phase
0dulation of the RF signal being processed or generated.
ais problem is especially significant when using ultrastable
_=quencies generated by modern atomic frequency standards
.g., oy [100 seconds] = 8.5 × 10 -13 for cesium). In order to
inimize the spurious AM and PM modulation of ultrastable
_quencies, the PARD on the associated power supply voltages
ust be minimized. Most commercial power supplies do not
duce the periodic variations, predominately at 60 Hz and
; harmonics, to a low enough level to use in ultrastable RF
circuitry. These periodic variations should be reduced below
the level of random deviation (noise). The need for a power
supply conditioner came about when the phase noise of a low
noise voltage controlled oscillator was measured and found to
exceed the specification for spurious signals. It was determined
that PARD from the power supply was modulating the RF
output signal.
Sidebands that are generated in frequency multiplier cir-
cuits as a result of PARD on the power supply voltage are of
particular concern because the power in sidebands, Pb' is
increased by,
Psb = 20 log (f2/fl) (1)
where fl is the input frequency and f2 is the output frequency
of the multiplier. For example, if a 5 MHz reference frequency
is multiplied to 10 GHz the sidebands will increase by 66 dB.
This increase in sideband power will often degrade the stability
of the desired high frequency signal to an unacceptable level.
https://ntrs.nasa.gov/search.jsp?R=19870019343 2020-03-20T10:15:19+00:00Z
ORIGINAL PAGE IS
OF POOR QUALIFY
The power supply conditioning circuit described in this
article takes advantage of the large difference in dynamic
impedance of constant current diodes and low voltage
avalanche zener diodes. This design uses the reference voltage
established by a constant current diode and a zener diode to
generate a I)C output voltage with low PARD.
II. Design
The circuit in Fig. 1 is capable of providing a DC reference
voltage having extremely low PARD for frequencies ranging
from DC to several KHz. The constant current diode (D1)
and zener diode (I) 2) in series form a voltage divider having
a very large division ratio for AC signals. Using the voltage
divider equation, the deviation, e, of the output voltage
caused by a deviation in the input voltage, el, will be,
where
r
z
e - e. (2)
o r +r z
C ;:
r = dynamic impedance of the zener diode, and
r = dynamic impedance of the constant current diode.
c
The dynamic impedance of the constant current diode can
be greater than 100 Kohms and the dynamic impedance of the
zener diode can be less than 10 ohms. If Eq. (1) is evaluated
for rc = 100Kohms and rz = 10 ohms the rejection ratio,
eo/ei, will be 10- 4 or -80 dB. Thus, the large dynamic impe-
dance of the constant current diode and the small dynamic
impedance of the zener diode, cause any deviation of the DC
voltage applied to the input of the voltage reference circuit to
be greatly reduced at the output of the circuit.
For the best results this circuit requires the use of a constant
current diode with the highest possible dynamic impedance
and a zener diode with the lowest possible dynamic impedance.
[1]. However, certain compromises must be made in designing
the circuit. The dynamic impedances of constant current
diodes have an inverse relationship to the current rating. As
the current ratings of constant current diodes go down, the
dynamic impedances go up. This makes it necessary to use a
zener diode which is designed to have a low impedance at a
low current so that the highest possible impedance ratio
consistent with good zener regulation can be obtained. Low
voltage avalanche zener diodes meet this requirement and have
low noise as well.
Since one of the requirements for achieving a maximum
rejection ratio in this circuit is to use the lowest possible
current, this circuit can only be used as a voltage reference.
The design described below uses additional circuitry t_
tain an output voltage with low PARD and to incre_
output current.
I
In the field effect transistor (FET) circuit (Fig.
reference is reproduced at the output using feedba_
operational amplifier (op amp), U 1 , used in conjunctio:
a field effect transistor, QI' increases the current cap_
The output voltage of the op amp controls the current tt,
Q1 in such a manner as to reproduce the reference vol_
the circuit output. Fluctuations on the drain voltage a,
reproduced at the source due to the high impedance be I
the drain and source.
For most applications the rejection ratio provided b
circuit is sufficient, but if even more rejection is require,
rejection ratio can be increased by connecting two stal,
series (Fig. 3).
III. Small Signal Analysis
I
A theoretical rejection ratio for this circuit can be ¢
mined using a small signal analysis. This analysis illust
which parameters limit the performance of the circuit, i
PARD is represented by an AC voltage source. Superpos
may be used to determine the effect of this source, by at
ing the source to different points in the model. In.this_
the AC source is first applied to the anode of the con._
current diode and then to the drain of the FET (Fi_
and5). !
The rejection ratios are defined in dB to be
V°ut]l
Rr I = 20log k--_j
and
Vout27
Rr 2 = 20 log _V--_-_nJ
[I (Rr'l (RrzllRr t = 20 log 0 exp \-2-0--f + 10 exp \ 20 f]
where
Rr I = rejection ratio with the AC source connected to
anode of the constant current diode,
Rr 2 = rejection ratio with the AC source connecte¢
the drain of the FET,
Rr t = totalrejection ratio,
Vout,= ACoutputvoltagewiththeACsourceconnected
totheanodeoftheconstantcurrentdiode,
l/'out2 = AC output voltage with the AC source connected
to the drain of the FET,
Vin = AC input voltage.
As shown in Eq. (5), the overall rejection ratio of this circuit
is approximately equal to the poorer of the two independent
rejection ratios.
IV. Analysis of FET Circuit
For purposes of analysis, the FET circuit was simplified
by removing the bypass capacitor. The analysis of the model
(Fig. 4) with the AC source connected to the anode of the
constant current diode, shows this rejection ratio to be largely
determined by the dynamic impedances of the constant
current diode and the zener diode. The following equations
may be arrived at from the model [2].
v2 - v,n V2 V: - Vouq
Rc + -_ + Rt n - 0 (6)
Vout, - V2 Vout,
R. =g,,Vgs- R
m eq
(7)
vg = A (v: - rout,) (8)
Vs = Vout x (9)
where
Vgs = A V2 - (A + l ) Vout 1 (10)
Rin = input impedance of operational amplifier
Rou t = output impedance of operational amplifier
A = gain of operational amplifier
R q = Rta//R °
Rla = load resistance
R = drain source resistance
o
Vg = ACgate voltage
Vs = AC source voltage
Vgs = AC gate to source voltage
gm = transconductance of the MOSFET
In the above, as well as throughout the remainder of this
article, the symbol R I//R 2 represents the lumped resistance
due to R, and R 2 being in parallel. In other words
1
R1//_,,2//D- 1 1
-- .1.
R, R 2
Combining Eqs. (6), (7), and (10) leads to
Vout]
l/in
Req(Ra)(1 + gmARin)
RcIReq+Rin+gmRinReq(A + I)-(_in +gmA) Req(Ra_
(11)
where R a = Rc//Rz//R _
With the assumptions
A>> 1
R >>R
C g
R. >>R
in g
R o >> Rta
Eq. (11) reduces to
Vout I R z
- (12)Vin R
C
The analysis of the model (Fig. 5) with the AC source
connected to the drain of the MOSFET shows this rejection
ratio to be largely determined by the transconductance and
drain to source resistance of the MOSFET, and the gain of
the op amp. The following equations may be derived from
the model.
Vout 2 Vout 2 Pin - Vout
__ + _ 2
R_a (RJ/R) + R_. g,. Vgs + Ro
(13)
V2 V2 Vout 2 - V2
+ =
R R R.
C Z In
(14)
Vg = A (V 2 - Vout2) (15)
Vs = Vout 2 (16)
Vgs = A V2 -(A + 1) Vou h (17)
Combining Eqs. (13), (14), and (17) leads to
gout 2
I/in
I
R
0
+gm(A + 1)
gmA(Ra)
R_
where
R a = RelIRzlIR _
and
R b = (RclIRz) +Rin
With the assumptions
(18)
A >> 1
R >> R
C z
R. >> R
In z
R >> 1
o
Rta > 1
Eq. (18) reduces to
V°ut2 1
= (19)
Vin gmARo
A component listing for an FET circuit (Fig. 6) that was
tested is given below.
D 1 1N5314 4.7 mA constant current diode
D_,
U 1
Q1
R
x
Rid
cl
D 3, D 4 LVA351A
OP-27
VN88AF
5.1 V zener diode
Low noise precision op amp
(PMI)
N-channel enhancement MOSFET
1 Kohm resistor
30 ohm resistor
1uF capacitor
The rejection ratio of this circuit was determined by adding
an AC voltage to the DC supply and measuring the AC voltage
present at the output of the power supply conditioner. A
-10 dBV AC signal was added to the input and rejection ratios
near -70 dB were measured for frequencies ranging from 1 Hz
to 10 KHz (Fig. 7). The input voltage was 22.0 V and the
output voltage 15.3 V, with an output current of 0.5A.
Equations (12) and (19) were used to compare this result
with the theoretical results, using values
A = 10-6
gm = 195 × 10-3 siemens
R = 3 Kohms
o
R = 50 Kohms
c
R = 15 ohms
z
The theoretical rejection ratio due to the constant current
diode and the zener diode is -70 dB, while that due to the
MOSFET is -175 dB. Thus in this case, the dynamic impe-
dances of the constant current zener diodes limit the rejec-
tion ratio to -70 dB.
V. Conclusion
The power supply conditioner described above provides a
simple and effective way to reduce the PARD found on the
output voltages of power supplies. A low noise voltage refer-
ence, consisting of a constant current diode and a low noise
zener diode connected in series, provides the basis for this
design. The rejection ratio of this design is determined by the
ratio of the dynamic impedances of the constant current
diode and the zener diode, and can be improved by increasing
this ratio and using lower noise zener diodes. Further improve-
ments can be made by connecting two stages in series. An
additional advantage of this power supply conditioner is that
it provides large current capabilities, making it a practical
addition to systems requiring power supplies with low PARD
down to DC.
References
[1] G. F. Lutes, "Stable Low Ngise Voltage Source," JPL DSNProgress Report42-47,
vol. July and August 1978, pp. 89-93, Jet Propulsion Laboratory, Pasadena, Calif.,
Oct. 15, 1978.
[2] R. A. Colclaser, D. A. Neamen, and C. F. Hawkins, Electronic Circuit Analysis Basic
Principles, John Wiley & Sons, Inc., USA, pp. 339-392, 1984.
D 1
e 0
D2
Fig. 1. Voltage refer.
ence circuit
D 1
Vin
l
I
I _ Q_ Vout
t Rld
Fig. 2. FET circuit
D1
D 2 '
Vin
Q
D3
_I_
Fig. 3. Two staged FET circuit
Q2
...,..@
i Rld
Vin
D
gmV_&_:0
Rc V2 Rin I S I
Voutl
<
41Rld
_I
Rout
Fig. 4. Small signal model with AC source on anode of
constant diode (Rc)
D• +v++tRo v+n
,,t L+ LR,o +°°'+
+ + +i
Rout
Fig. 5. Small signal model with AC source on drain of FET
q
D 2
D 4 /'_(
Vin
1
Rx
i
J
Q1
--.-,-.o Vou t
Rld
C1
Fig. 6. Example FET circuit
-50
-55
m
o" -60
k-
,<
z
O
C.)
N -65
/
_70 j
-75
100 101 102 103
FREQUENCY, Hz
104
Fig. 7. Measured rejection ratio vs. frequency for FET circuit


Power supply conditioning circuit

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