An introduction to the major issues encountered in the readout of imaging detector arrays in the infrared are presented. These include circuit issues such as multiplexing, buffering, and noise, as well as materials issues. Future directions in infrared readout electronics will also be discussed. These include on-chip signal processing and advanced hybridization schemes. Finally, recent work at Columbia on 2DEG-charge coupled devices for IR detector multiplexing are described

Fossum, Eric R.

English

NASA Technical Reports Server

III-2 N91-14387
ISSUES AND DIRECTIONS IN IR DETECTOR
READOUT ELECTRONICS
Eric R. Fossum
Department of Electrical Engineering
Columbia University
New York, NY 10027
Abstract
An introduction to the major issues encountered in the read out of
imaging detector arrays in the infrared will be presented. These
include circuit issues such as multiplexing, buffering, and noise, as
well as materials issues.
Future directions in infrared readout electronics will also be
discussed. These include on-chip signal processing and advanced
hybridization schemes. Finally, recent work at Columbia on 2DEG-CCDs
for IR detector multiplexing will be described.
117
https://ntrs.nasa.gov/search.jsp?R=19910005074 2020-03-19T20:38:57+00:00Z
Issues in FPA Readout Electronics
Eric R. Possum
Dept. of Electrical Engineering
Columbia University
NY NY 10027
ERF
Outline
1. Present Imager Readout Architectures
2. Special Problems in LWIR Readout
3. GaAs CCD Readout
4. On —chip Signal Processing
ERF
118
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DISTANCE
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119
4-PHASE CHARGE TRANSFER
120
Schematic illustration of a charge-coupled device (CCD)
iraager read-out structure.
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INTEGRATING INPUTS
1. DIRECT INJECTION
Qsig-$'(t)dt
2. GATE MODULATION
Qsig =
COULD BE SUBTHRESHOLD
OR WEAK INVERSION
OR INVERSION
123
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SiO 2 - -
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(AR COAT)
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256 f->^
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255
HORIZONTAL CCD Z
OR
FLOATING
DIFFUSION AMP
Fig. 3. Schematic diagram of 256x256 element IR-CCD image
sensor.
Kimata, et al. Opt. Eng 16(3) 211 (1987)
124
(0
1__L
.1
Output
KW
Output
'0
— Output
: CHW
Output
Fig. 2. Various detector readout structures: (a) gate readout (GRO);
(bTgs'ce-coupled readout (GCRO) to. CCD; (c) direct-injection (D!) cur-
rent readout; (d) direct-injection ancillary current (D1AC) readout;
(e) direct-injection bipolar (DIB) current readout; (f) direct-injection
bipolar ancillary current (DIBAC) readout; (g) buffered direct-injection
(BDI) current readout.
Bluzer and Jensen Opt. Eng. 2 6 ( 3 ) 241 (1987).
125
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WTSCTOH SUBSTRATE
omcrou W/TH
• UM*
SH.ICON CCO SlGMAt.
OOP
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REGISTER READOUT RECISTED
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| ^-IMPLANTED •. REGION
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cco INPUT NODE—I PASSIVATION INDIUM
BUMP
(• CCD MUlimtXt*
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Fig. 8. Backside-Illuminated hybrid FPA.
FL
Li ^~r^
VURAL
—DIG —sMitio — $»o*i —vi —*i _«i
Fig. 6. Direct injection input circuit schematic lor 64 x 64 mulliplexef.
/ OPTICAL ENGINEERING / March 1987 / Vo». 26 No. 3
126
Comparison of CCD Technologies
u
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310
D
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11..
10
III-V CCOS
J 2DEG CCO
GoAa SCHOTTKY GATE
3
I
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SURFACE CHANNEL
TRENCH CCO
30 BURIED CHAN
VIRTUAL PHASE
IR Photon Flux
3-5 urn 5 x 10
8-12 urn 3 x 10
14
ie
F/3.0
5 10 15 20
Bucket Voltage
Schematic illustration of a MOS-CCD iraager read-out
structure.
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127
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YDD
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A
(a) (b)
Fig. 5. Reset integrator input circuit: (a) functional block diagram,
(b) MOSFET implementation.
VDD
AMP
VDD
Fig. 6. Buf fered common gate input circuit: (a) functional block
diagram, (b) MOSFET implementation.
Lockwood and Parrish, Opt. Eng 2.6(3) 228 (1987) .
128
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Fig. 2. Simplified schematic of the direct readout circuit used for
this array.
Fig. 5. Representation of the voltage across a single pixel during
an integration Interval at the detector node.
Fowler et al. Opt. Eng. 26(3) 232 (1987). ORIGINAL PAGE IS
129 OF POOR QUALITY
V,
S,(f, S-,<0
' s i f i
Fig. 8. Carrier modulation scheme used to upconvert detect
signals to higher frequencies where MOSFET noise is low.
Dciccior
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Fig. 9. Buffered common gate readout input circuit using chopr
stabilization to reduce detector bias o f f s e t s and amplifier 1/f noi:
10n ^=r
=^~=. Chopper g
- Stabilized -
3' • -~ • • \ \ \ \ i~l •HlC^liili
R A (Qcm2 )
o
Fig. 10. Projected chopper-stabilized InSb focal plane perfc
mance.
Lockwood and Parrish, Opt. Eng 26(3) 228 (1987).
130
IMAGE ACQUISITION
+ IMAGE PROCESSING
FOCAL PLANE IMAGE PROCESSING
WHY
NOISE
DISTORTION
POWER
SIZE
RELIABILITY
COST
WHY NOT
YIELD
CHIP SIZE
COOLING
NON-UNIFORMITY CORRECTION
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bVector
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Serial Shift Register Output
Amplifier
131 OR16SNAL PAGE IS
OF POOR QUALITY
NON-UNIFORMITY CORRECTION
GAIN
SIG CCD
MDAC
REF ^ CCD
MDAC
OFFSET
MULTIPLYING CCD D/A CONVERTER
R
R/2 R/4
Bl J B2
R/8
>RB
B3
132
Fig. 2. Photograph of (a) serial recursive circuit and (b) single stage of pipeline circuit.
133
PAGE IS
OF POOR QUALITY
Fig. 3. Oscilloscope photograph showing analog output of pipeline programmable gain control circuit in
response to a digital ramp (upper trace) and MSB of digital control word (lower trace).
+ 4-
DIFFERENTIAL ERROR
0
4B15-7
Vclk=10 V
2.4 usec
Digital Control Word 1023
Fig. 4. Differential linearity error of pipeline circuit. Note that 1 LSB tic mark corresponds to 1/1024 of
full scale.
134
CCD Programmable Gain Control Circuit
Performance Summary
Technology
Circuit Size
Resolution
Integral Linearity
Differential Linearity
Clock Voltage
Bucket Cap. (electrons)
Power (1 03 conv/sec)
Max. Conversion Rate
Pipeline
3pm CCD
0.4 mm2
1 0 bits
8 bits
8 bits
1 0 volts
5x1 06
2pW
>8x106/sec
Serial
3pm CCD
0.013mm2
variable
6 bits
6 bits
10 volts
5x1 06
2pW
>0.5x106/sec
Spatial ly F Architecture
Pixel-
Processor
135 OF POOR
FPA CCC POWER CONSIDERATIONS
TO TRANSFER 1 BUCKET (HALF FULL) AV = 10 VOLTS
ENERGY = 8 pj
ARRAY WITH 1500 PEs OPERATING IN PARALLEL
12 nJ
SAY EACH INSTRUCTION REQUIRES 10 TRANSFERS,
SAY 100 INSTRUCTIONS PER PIXEL TO PREPROCESS
12 nJ PER FRAME
SAY 1000 Hz FRAME RATE*
12 mW CHIP DISSIPATION
ADD IN DRIVERS, PARASITICS, MULTIPLY BY 2
25 mW
FOR 1 kHz REAL TIME PREPROCESSED IMAGERY
' AT 100 nsec/TRANSFER, CAN OPERATE AT 1MHz INSTRUCTION
RATE, OR 10 kHz FRAME RATE POSSIBLE
NOISE CONSIDERATIONS
SAY BIAS = 10 V —»- 8 VOLT BUCKET
-250.000.000 ELECTRONS/HOLES
SAY WANT 8-BIT EQUIVALENT ACCURACY W/ SNR = 4 ON LSB
—»- MAXIMUM NOISE ~ 250.000 CARRIERS
NOISE SOURCES:
1) CAPACITIVELY COUPLED CIRCUITS
"RMS = (kTC^ 1°00 CARRIERS
2) TRANSFER
1/2
"RMS = (2 ER) £ 5000 CARRIERS
0.05^
3) INTERFACE
(1 .4 kTD|TAE)1/2< 200 CARRIERS
CCC PROGRAM, SAY 50 TRANSFERS AND 10 FILL & SPILLS
—». RMS 35,000 CARRIERS
136
WHY GaAs CCDs ?
Device Structure dV dQ
Cg+Co
Schottky
* rTTTI \777\ 17773 P777 P7>\7 A Ohmic
n
.
- GaAs
. baAS ::::::::::
J_Co
Features
High Electron Mobility
High Transfer Speed
High ft Transistors
Wide Bandgap
Radiation Hard
Low Noise
Semi-Insulating Substrate
Low Parasitic Capacitance
Mesa Isolation
Compatibility with III-V Detectors
137
BAND DIAGRAM OF GaAs CCD
Vg 1n-GaAs S. \. GaAs
Without Signal Charge
With Signal Charge
 x Qsig=qNd A x
Vg > 0
138
Capacitive-Gate CCD
rG1< /G2
 T
Y////////X \y///////x V///////A
n - GaAs
S.I. GaAs
Resistive-Gate CCD
V
139
Silicon CCD
SiO- p-Type Silicon
2DEG CCD
AIGaAs S. I. GaAs
140
BAND DIAGRAM OF 2DEG CCD
AIGaAs Undoped-GaAs
Vg
Without Signal Charge
VgX)
With Signal Charge
VgX)
141
2DEG RGCCD
Device Structure
INPUT G1 G2 G3 01 02 #3 04 04 OUTPUT
L i i i i i LL^ ,
ttttttttl | CERMET n+GaAs
AIGaAs
unit/ran o * UNDOPED AIGaAsUNDOPEO GaAs
SL BUFFER
S.I. GaAs SUBSTRATE
Features
High Electron Mobility
High Transfer Speed
High Performance 2DEGFET
Large Dynamic Range
ns > 1x1012/cm2
High Sensitivity Input
Enhanced
Low Temperature Performance
142
OPERATION OF 2DEG RGCCDs
Room Temperature
4 Phase Clocking, 32 Stages (128 Transfers)
1 urn Electrode Width, 4 urn Spacing, 100 urn Channel Width
Uniform-Doped 2DEG RGCCD
CTE = 0.999 At 1 GHz
Planar-Doped 2DEG RGCCD
CTE > 0.999 At 133 KHz
Advances in 2DEG CCDs
Year
1982
1983
1990
1990
1990
Group
Rockwell
Rockwell
Columbia
Columbia
Columbia
Channel | Gate
Layer
Material
AIGaAs
/GaAs
AIGoAs
/GaAs
AIGaAs
/GaAs
AIGaAs
/GoAs
(S-Doped)
InAIAs
/ InGaAs
(8-Doped)
Structure
Copacitive
Copocitive
Resistive
Resistive
Resistive
Gap
Size
2
1
N/A
N/A
N/A
Gate
Length
X
Width
(um)
40
X
400
5
X
5
X
100
5
X
100
5
X
100
Clock
Freq-
uency
<83 KHz
< 83 KHz
13 MHz
- 1 GHz
130 KHz
- 1 GHz
CTE
0.98
< 0.9
0.989
0.999
> 0.999
Test
Condi-
tions
300 K
300 K
77 K
300 K
300 K
143
ORIGINAL PAGE IS
OF POOR QCMJ./TY
DIRECT DETECTION
HBWJ n n •Cermet
03 ,04 ,01 ,02 ,03X04 ,01
'm
JPL
LHd
351D RROR JIS 1SRD
144
INDIRECT DETECTION
Direct Injection
V,
Cermet
G1 G2 G3 GT GS
INDIRECT DETECTION
Gate Modulation
145
GaAs CCD MULTIPLEXER DESIGN
Linear Arrays (32 stages. RGCCD, CGCCD)
Direct Detection
Indirect Detection
Direct Injection
Gate modulation
2-D Arrays (32x32. RGCCD)
Direct Detection
RESEARCH ISSUES
• Leakage Current Reduction
Transport Mechanisms
Materials Quality
Structure
• Dynamic Range
Pinch Off Voltage
Leakage Current
• New Material System
(InAIAs/lnGaAs)
Higher Electron Mobility
Larger Dynamic Range
146
Planar-Doped In Al As / In Ga As RGCCD
0.52 0.48 0.53 0.47
I
1
InP
• High Mobility(^20.000 _«?_._ at77K)
Vs
• Large Sheet Carrier Density
e SWIR Direct Detection
o Compatible with Fiber-optic
Integration
Present and Future Issues
in Readout Electronics
Hybridization Technology
center-to-center spacing
array size
buttobilty
reliability
Multiplexer Material
thermal match
low 1/f noise devices
On—Chip Signal Processing
random event correction
detector non-uniformity correction
image processing
signature recognition
4/13/90 EW
147


Issues and directions in IR detector readout electronics

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