Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid state, block access, VLSI memory which offers the potential of 1 Gbit/sq cm areal storage density, data rates of hundreds of megabits/sec, and submillisecond average access time simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBLs are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of BVL pairs are used to store binary information. At present, efforts are being directed at developing a single chip memory using 25 Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. The current design architecture, functional elements, and supercomputer simulation results are described which are used to assist the design process

Katti, R. R.

Stadler, H. L.

Wu, J. C.

English

NASA Technical Reports Server

N91-24051
INTEGRATEDVERTICALBLOCH LINE (VBL) MEMORY
R. R. Katti, J. C. Wu, and H. L. Stadler
Jet Propulsion Laboratory
California Institute of Technology
Pasadena, CA 91109
ABSTRACT
Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid-state, block-access, VLSI
memory which offers the potential of 1 Gbit/cm 2 areal storage density, data rates of hundreds of megabits
per second, and submillisecond average access times simultaneously at relatively low mass, volume, and
power values when compared to alternative technologies. VBLs are micromagnetie structures within
magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The
presence or absence of VBL pairs are used to store binary information. At present, efforts are being
directed at developing a single-chip memory using 25 Mbit/cm 2 technology in magnetic garnet material which
integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a
memory. This paper describes the current design architecture, functional elements, and supercomputer
simulation results which are used to assist the design process.
INTRODUCTION
Vertical Bloch Line (VBL) Memory _' _ 3 is a solid-state, radiation-hard, nonvolatile, block access,
magnetic VLSI memory. Research and development efforts for this novel memory are being pursued in the
United States, Europe, and Japan. Table 1 shows the potential storage density that is achievable with VBL
memory. The densities are a function of stripe width and line feature width, which are defined respectively
by the magnetic garnet material and the lithographic process.
In a VBL memory, information is stored using VBL pairs in magnetic stripe domains in garnets. The
presence or absence of a Vertical Bloch Line pair in a bit-cell location defines a binary "l'and "0,"
respectively. Input to the chip is performed by converting currents into magnetic bubbles and then into VBL
pairs. Output sensing is performed by converting VBL pairs into magnetic bubbles and sensing magnetic
bubbles magnetoresistively.
PRESENT DEVICE DESIGN
Fabrication
The present design uses the magnet garnet, (BiYGdHoCa)3(FeGeSi)50, 2, as the storage medium. The
thickness, stripe width, collapse field, saturation magnetization, and anisotropy field of the film is
approximately 2.4# m, 2.4# m, 230 Oe, 450 Oe, and 1800 Oe, respectively. The film is grown epitaxially on
a non-magnetic gadolinium-gallium-garnet (GGG) substrate. These films are transparent but also have a
large Faraday rotation, so that magnetic stripes, magnetic bubbles, and, under certain conditions, VBLs can
be observed magneto-optically with polarized light using the Faraday effect in a polarized light microscope.
The magnetic garnet has perpendicular magnetic anisotropy so that the magnetization lies perpendicular
to the film plane, with the bulk of the film magnetized in one direction, and the stripes magnetized in the
opposite direction. A magnetic domain wall is the boundary between the stripe's magnetization and the
magnetization of the rest of the film. A twist of magnetization in the domain wall in the plane of the film is
a VBL, and two such twists form a VBL pair. If the chirality, or sense of rotation, of the VBLs in the wall is
the same, the VBL pair is stable, with a size calculated to be much less than 1 # m. The VBL pair is bound
together energetically by VBL demagnetizing field energy and magnetic exchange energy.
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https://ntrs.nasa.gov/search.jsp?R=19910014738 2020-03-19T17:45:10+00:00Z
The present device is divided into four main functional areas. First, the VBL storage area is designed to
confine and stabilize stripe domains. Second, read/write gates are needed to convert VBLs to bubbles and
vice versa. Third, a major line is needed for propagating bubbles which are used for input and output.
Fourth, the output detector is needed for generating the output signal voltage. A sample architecture for a
VBL chip is shown schematically in Figure 1.
The present device is built with ten mask layers as shown in Figure 2. Three metal mask layers are used
for providing the contact pads and conductors which control the strip generator, read/write gates, bubble
generator, and major line. SiO 2 and photoresist are used for insulating metal layers, and a window mask is
used to open vias and contacts when needed between metal layers. Two ion implantation mask steps, using
150 keV Ne+ ions at a dosage of 4 x 10 Is ions/cm 2, are used so that, after etching, grooves which are 0.2/z
m and 0.4 _t m thick are created. These grooves create stable locations in the garnet film for VBL stripe
domains. An additional ion implantation mask layer is used in the major line to inhibit VBL formation in
the input/output bubbles. A permalloy (Nio.sFe0. 2) mask deposition is used to develop a magnetoresistive
sensor which senses magnetic bubbles at the output and produces output voltages. A cobalt-alloy (i.e., CoP0
mask deposition is used for creating bit cells for VBL pairs along the walls of stripe domains. In test chips,
a 5 nm thick Cr mirror layer is used to assist in stripe, bubble, and VBL observations using the magneto-
optic Faraday effect during testing.
Supercomputer simulation#' s which compute the effect of magnetic fields on magnetic domains, such as
with stripe grooving, the major line, and the major line expander, are used heavily to assist in device design.
VBL chip layouts are performed on an HP workstation and IBM PC/AT computers. Layouts are converted
into fabrication masks using CIF and GDS II formats.
Stripe and Bit Stabilization
Data in the form of VBL pairs are stored in the domain walls of array of strip domains as depicted in
Figure 3. The stripes are physically located in grooved regions in the garnet, as shown schematically in
Figure 1 and in the design layout in Figure 4. The grooving allows selecting the bias field so that stripes are
stable when the other chips functions, including the major line, are operating. The demagnetizing field
produced by the bias field at the edge of grooved regions also serves to hold the stripe end and produce a
stabilizing, effective edge-affinity magnetic field. Results from a supercomputer simulation of the formation
of stable stripes in grooved garnet are shown in Figure 5. The computations were performed at 1 nsec time
steps, and the computed stripe domain shape is shown at 40 nsec intervals.
Bit stabilization is used to stabilize VBL pairs along the stripe, as shown in Figures 1, 3, and 4. A
periodic potential is placed along the stripe by an array of CoPt bars. For the CoPt, the saturation
magnetization, coercivity, geometry, and spacing from the garnet are chosen to provide a sufficient field of
approximately 50e at the VBL stripe. This field value is currently considered to be enough to provide fields
which create potential wells for the VBL pairs without disrupting the VBL pairs and moving stripes away
from their groove-stabilized positions. The computed bit stabilization field profile at the end of an array with
a 2/z m bit period is shown in Figure 6. The distance between the CoPt and the garnet film is a parameter
in the plot. The periodicity in the field profile is clearly evident.
Propagation of the VBL pairs, around the bit cells and to the read/write gates, can be achieved in two
ways. First, a vertical pulse field can be applied which presses, or rocks, the stripe against the groove wall
which gyrotropically causes VBL pairs to propagate down the stripe. Second, an in-plane field can be
applied which directly causes VBL pairs to advance along the stripes' walls.
Read/Write Gates
Read/write Gates are used to convert VBL pairs in stripes into bubbles during the read process, and to
convert bubbles into VBL pairs during the write process. It is necessary to read and write both "Us'and
"0's'correctly. Nondestructive readback is achieved by using a current in conductors to bring the end of a
87
stripe out of its groove into the read/write gate and into the presence of another conductor. If no VBL pair
is present at the end of the stripe, the sense of the magnetization direction in the stripe wall causes the stripe
to be difficult to chop with the field from a conductor because of the effect of exchange energy. The stripe is
then returned to its stable position in the grooving. However, if a VBL pair is present, one VBL would be
brought into the read/write gate while the other VBL would remain in the grooving. Hence, the chirality of
the strip walls would be in the same direction which would readily allow the stripe to be chopped. The
chopped portion of the stripe becomes a bubble, which is them propagated to the output for sensing, while
the stripe returns to the grooved region. The chopping process recreates a VBL pair in the stripe which
leaves the initial information intact.
Writing is achieved by bringing a bubble from the nucleator and major line to the desired read/write
gate. If a bubble is present,m when the stripe is subjected to a field to bring it into the read/write gate, the
stripe does not get drawn into the read/write gate because of magnetostatic repulsion between the bubble
and the end of the stripe. Therefore, no writing to the stripe occurs. But if a bubble is not present, the
stripe is brought rapidly into the read/write gate which inserts a VBL pair into the stripe, end the stripe is
then allowed to relax into the grooving.
M.aior Line and Output Detector
The major line consists of a bubble nucleator for converting input signal currents into bubbles, a track
for propagating bubbles from the nucleator to the read/write gates and from the read/write gates toward the
output, an output detector for converting the demagnetizing field from bubbles into output voltages, and an
expander which is used to stretch a bubble to a desired length to provide a satisfactory signal-to-noise ratio
at the output.
A hairpin conductor is used for the nucleator. When a current is applied, such a conductor produces a
magnetic field which is concentrated at the center of the hairpin. This field is used to generate bubbles
which are used to transmit binary information to the VBL stripes via the read/write gates.
The propagation track in the major line consists of two levels of conductors. Each conductor is a
sepentine arrangement of hairpin conductors which provide local magnetic field variations which form
"waves'of stable positions for the bubbles down the track. The conductors are physically phase shifted by
90 ° to effect propagation. The principle of operation of the major line is shown in Figure 7. The layout of
the major line track, along with the bubble nucleator and two read/write gates and grooves, is shown in
Figure 4.
The output detector consists of a rectangular strip of permalloy, which is magnetoresistive. When the
fringing magnetic field from a magnetic bubble affects the sensor, the sensor's resistance changes. When a
reference current is issued to the sensor, the presence or absence of a bubble induces two different voltage
levels which define binary "l's'and "O's." If it were necessary to maximize common-mode rejection from
stray magnetic fields, two magnetoresistive sensors, including the actual sensor and a dummy sensor, can be
used which allow signals to be measured differentially. Signals from the magnetoresistive sensor are
increased if longer elements with greater electrical resistance are used. Bubbles can be stretched in length,
to provide additional magnetic fields for the lengthened sensor, by widening the bubble track as the bubble
approaches the sensor. The combined output sensor and expanding major line are shown in Figure 8, in
which only one propagation metal layer in the major line is shown for clarity. Shown in Figure 9 is a
supercomputer simulation, shown at 40 nsec intervals after being computed at 1 nsec intervals, of a bubble
being stretched and then unstretched as it passes through the expander and detector.
EXPERIMENTALRESULTS
Sample experimental results of chip functions from past designs are now presented. _v These data were
taken on test chips using a 4.76 _t m thick (BiYSmLu)_(FeGa)sOt2 garnet film with a saturation
88
magnetization of 200 Oe, zero-field stripe width of 4.67/_ m, characteristic length of 0.61/_ m, domain wall
mobility of 350 em/sec/Oe, anisotropy field of 1350 Oe, coercivity of 1.10e, and collapse field of 100 Oe.
Figures 10 and 11, respectively, show stabilized stripes in grooves near read/write gates at the end of a
groove, and near the center of the stripe groove near the stripe nucleator. The stripes are observed, with
polarized light using the magneto-optic Faraday effect, as white strips against a darker background. The
dark bars running perpendicular to the stripes are the cobalt bit-stabilization bars as described in Figures 1,
3, and 4.
Figure 12 shows nucleated bubbles, as white spots, in the major line as they propagate down the track.
Bubbles and stretched bubbles in the expander portion of the major line near the output detector are shown
as white sports and strips, respectively, in Figure 13.
CONCLUSION
VLSI designs, simulation results, and experimental results have been presented which describe current
work on the storage and input/output functions for solid state, high density, nonvolatile, radiation hard, block
access Vertical Bloch Line (VBL) Memory. Such a memory offers the potential of achieving 1 Gbit/em 2.
Three metallizations are used along with three ion implantation steps, one permalloy magnetoresistive sensor
deposition, and one CoPt bit-stabilization deposition. Previous and current experimental results and
supercomputer simulations indicate that individual storage, read/write gate, and input/output functions are
feasible. Present work is aimed at integrating all necessary memory functions on a single chip to achieve
simultaneous operation, a unique operating point, and a fully-functional single chip memory.
ACKNOWLEDGEMENTS
The research described in this paper was performed by the Center for Space Microelectronies
Technology, Jet Propulsion Laboratory, California Institute of Technology, and was sponsored in part by the
Strategic Defense Initiative Organization Innovative Science and Technology Office. The use of the
JPL/Caltech CRAY X MP/18 for performing portions of this work is acknowledged.
REFERENCES
. S. Konishi. "A New Ultra-High-Density Solid State Memory: Bloch Line Memory," IEEE
Transactions on Magnetics, Vol. 19, No. 5, pp. 1838-1840,September, 1983.
. T. Suzuki, et al. "Chip Organization of Bloch Line Memory," IEEE Transactions on Magnetics, Vol.
22, No. 5, pp. 784-789, September, 1986.
. H. Matsutera, et al. "Design and Characteristics for Vertical Bloch Line Memory Using Ring-
Shaped Domain," IEEE Transactions on Magnetics, Vol. 23, No. 5, pp. 2320-2325,September, 1987.
. J. C. Wu. "Solid-State Magnetic Devices: Magnetic Bubble Logic Devices and Vertical Bloch Line
Memory," Ph.D. Thesis, Carnegie Mellon University, August, 1986.
. N. Hayashi and K. Abe. "Computer Simulation of Magnetic Bubble Domain Wall Motion,"
Japanese Journal of Applied Physics, Vol. 15, No. 9, pp. 1683-1694,September, 1976.
. J. C. Wu, et al. "Major Line Operation in Vertical Bloch Line Memory," Paper FP-10, Accepted for
Presentation, 1990 Magnetism and Magnetic Materials Conference, San Diego, CA, October, 1990.
. J. C. Wu, et al. "Stripe Stabilization in Vertical Bloch Line Memory," Paper FP-9, Accepted for
Presentation, 1990 Magnetism and Magnetic Materials Conference, San Diego, CA, October, 1990.
89
L¢.¢_= -Lc.,_0J_ma
Sw - 5 _m: 10 MbitrJcm 2 20 Mbits/cmZ I00 Mbit_cm 2
Sw - 2 pro: 25 I_,g_lsJcm2 50 Mbits/cm 2 250 Mb_l_cm 2
Sw ,=1 p.m: 50 Mbils/cm z f00 Mbits/cm 2 500 MbitgJcm2
Sw -0.5 gin: 100 Mbits/cm 2 200 Mbits/cm 2 1000 Mbils/cm 2
Sw - 0.25 p.m: 200 Mbits/cm 2 400 Mblis/cm 2 2000 Mbil_cm 2
Table 1: VBL Sloraga Density as a Function of Stripe Width, Sw, and
Line Feature Size, LI. Stor'_ge den_ty is inversely I_oportlonal tO 2SwLf.
Cuunter.eTockwlse stripe wlthou! static In-plane field
-*._ ,%'-_ _ t" *, _--_
'" :,, _, M,_onellzotiml
Figure 3: Schematic of VBL Stripe Storage Structure.
/
Glunet Groovlnq [m ;-Sit Periodic
Stripe Slabilizalion S/_'._R C,_#
Left
Male,L_,
Line
f_
/ \Hard Magnetic Fi]ml
S_mp/eVBL Io1' Gil Slabillzltlon Right
bit Positions\ / Ms,or
/_/__! / Minor Loops LI._n•
Bubble
Figure 1" Schematic VBL Architecture.
I I!I lll!!tlil!l(lllll!I!llliIII
Jl:l141!ltti II!1
I 11111lltl!!!illtllfl!!ili i!illlltlitll!li
i 'i'ii ii
.t .....
Cut-away View of VBL Memory Devices
Process Option
Figure 4: Layout of VBL Chip Nucleator, Dual-Conductor Major Line, and r
Read/Write gates and Two Stripe Grooves.
1 _lm scralch prolaclion pholore_;ist
0. f lira per,'nalloy
0.6 txm photoresisf Insulator
0.6 lxrn !ohotoresist ]nsui_forI
I _'____'_/_f_'_'/S/_"/_'_'_ 0.3 lira aluminum"
. 500 _ COPI _illi![lllltlllUfllllllrlllllllilliiillllJlUillilllll
I 0.6 IJm t:lholoresist Insulator
50 A lchromium for planarization photoresist /
magn to oplic testing
to-opl*o 0.1 _m silicon dioxide insulator
2 _.m gannet
Figure 2: Cross-Section of the Current VBL Fabrication Process.
9O
I I
Figure 5: Supercomputer Time-Evolution Simulation Results of
Stable Stripe Formation in a Grooved Garnet.
ORIGINAL PAGE IS
OF P_)O_ QtlAUTY
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)_._!._._...?...i...!l.._.._-.___, !_! !_! ,_,, .... :,
 f:2iiii!iii iii!iiiiiii!iil]iiiiiii!i!i]iii[iii iii!iii[iiiiiii!
The Dare;_el _ars are lnfln]teJy Ion 0 Se t_! y-lxl$ r|lI_ maw*12.194500, mln-m21167341
el=tO O, a_-$1.O_ ci=O00, c2-0,04, S_= 1,0. 40_NS= _000 $, xao 4000, =C-24000
Za= l,OaO. _a- 3.040. grt_x-JO, gP_Z- 4. NB=LO0. zn-_]ane component,
Figure 6: Computed Periodic Magnetic F_eld Profile of
VBL Bit-Stabilization Wells.
Propagation of Bubbles Using Current
(m) (b) (¢) (d) (e)
Figure 7: Principle of Bubble Propagation in a Dual-Conductor Major Line. r'--P
\
\
Figure 8: Layout of VBL Expander and Output Detector.
ORIGINAL PAGE IS
_ OF POOR QUALITY
91
Figure 12: Major Une Under Operation Near the Center of the Major Track.
FTgure 9: Supercomputer Time-Evolution Simulation of an
Expanding Bubble in the Major Line Expander and Output Detector.
Rgure 13: Major Une and the Major Une Expander Under Operation.
F'_ure 10: Photograph of Stable Stripes Near the Read/write Gate end in
a VBL Test Chip.
Rgure 11: Photograph of Stable Stripes at the Stripe's Center, Near the
Stripe Nucleator in a VBL Test Chip.
92
ORIGINAL PAGE IS
OF POOR QUALITY
SESSION C - ENVIRONMENTAL TECHNOLOGY
Wednesday November 28, 1990
Physical/Chemical Closed-Loop Water Recycling
Water Quality Analyzer
New Research On Bioregenerative Air/Water Purification Systems
Environmental And Facilities Management System (EMFS)
The Land Analysis System
Potential Commercial Use Of EOS Remote Sensing Products
93


Integrated Vertical Bloch Line (VBL) memory

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