Ultra-dense magnetoresistive mass memory

Abstract

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis