The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter

Askew, Ray

Bromstead, James

Johnson, R. Wayne

Weir, Bennett

English

Semiconductor power devices are typically rated for operation below 150 C. Little data is known for power semiconductors over 150 C. In most cases, the device is derated to zero operating power at 175 C. At the high temperature end of the temperature range, the intrinsic carrier concentration increases to equal the doping concentration level and the silicon behaves as an intrinsic semiconductor. The increase in intrinsic carrier concentration results in a shift of the Fermi level toward mid-bandgap at elevated temperatures. This produces a shift in devices characteristics as a function of temperature. By increasing the doping concentration higher operating temperatures can be achieved. This technique was used to fabricate low power analog and digital devices in silicon with junction operating temperatures in excess of 300 C. Additional temperature effects include increased p-n junction leakage with increasing temperature, resulting in increased resistivity. The temperature dependency of physical properties results in variations in device characteristics. These must be quantified and understood in order to develop extended temperature range operation

NASA Technical Reports Server

33 c> /
SILICON DEVICE PERFORMANCE MEASUREMENTS
TO SUPPORT TEMPERATURE RANGE ENHANCEMENT
Cooperative Agreement NCC3-175
NASA
Lewis Research Center
Cleveland, Ohio
Semi-Annual Report
May 7, 1990 - November 7, 1990
Prepared by"
James Bromstead
Bennett Weir ..="
R. Wayne Johnson, Principal Investigator
Ray Askew, Principal Investigator
February 11, 1991
Auburn University
Center for the Commercial
Development of Space Power
231 Leach Center
Auburn, AL 36849
(NASA-CR-I_7904) SILICON DEVICF PERFORMANCE
MEASUREMENTS TO SUPPORT TEMPERATURE RANGE
ENHANCEMENT Semiannual Report, ? May - 7
Nov. 19Q0 (Auburn Univ.) 21 p CSCL 09A
N91-18352
Unclas
G3/33 03303B1
https://ntrs.nasa.gov/search.jsp?R=19910009039 2020-03-19T19:43:56+00:00Z
Performance of Semiconductor Power Devices at High Temperature
INTRODUCTION
Semiconductor power devices are typically rated for
operation below 150°C. Space based power systems typically
generate high currents at low voltages, with attendant
temperature increases. To reduce losses and weight associated
with such requirements, it would be advantageous to locate the
power conversion and conditioning electronics as close to the
primary source as possible. Location, however, is limited by the
local temperature generated by the power source. Electronics
capable of operating at higher temperatures could be placed
nearer the power source. In addition, conversion and conditioning
electronics produce significant heat which must ultimately be
removed. Enhanced temperature electronics would result in a
higher heat rejection temperature for the thermal management
system resulting in a reduction in the size of the thermal
radiators, decreasing launch weight.
Little data are available forpower semiconductors over
150°C. In most cases, the device is derated to zero operating
power at 175°C. At the high temperature end of the temperature
range, the intrinsic carrier concentration increases to equal the
doping concentration level and the silicon behaves as an
intrinsic semiconductor. The increase in intrinsic carrier
concentration results in a shift of the Fermi level toward mid-
bandgap at elevated temperatures. This produces a shift in
devices characteristics as a function of temperature. By
increasing the doping concentration higher operating temperatures
can be achieved. This technique has been used to fabricate low
power analog and digital devices in silicon with junction
operating temperatures in excess of 300°C. Additional temperature
effects include increased p-n junction leakage with increasing
temperature, resulting in increased resistivity. The temperature
dependency of physical properties results in variations in device
characteristics. These must be quantified and understood in order
to develop extended temperature range operation.
LABORATORY SETUP
A variety of equipment is needed to characterize the
relevant devices parameters. The instrumentation in the lab is
linked using an IEEE-488 (GPIB) interface and a PEP-301 (80386-16
compatible) computer, for automated testing and data acquisition.
Table 1 lists the equipment (hardware and software) available to
perform the tests and the GPIB address of each device. The
general layout of the lab is shown in Figure I. Connections to
the DUT (device under test) are made using Teflon insulated wire,
to withstand temperatures up to 200°C.
1
DEVICES UNDER TEST
The devices were chosen for similar current carrying
capability (approximately 50A). (see Table 2)
DEVICE MEASUREMENTS
The software for each of testing procedures included the
same temperature control subroutine. This subroutine instructed
the test chamber to bring the ambient temperature within +/-0.2°C
of the desired test temperature. This temperature was then held
for 5 minutes to allow the entire device to achieve the ambient
chamber temperature. The individual test was then performed and
the temperature raised. The test temperatures ranged from 20°C to
200°C in 10°C increments.
Test performed using the TEKTRONICS 371 high power curve
tracer utilized pulse current measurement. The pulse rate (half
amplitude pulse width) employed by the curve tracer is 250us +/-
10%, with a rise fall time of 40us to 120us. The repetition rate
is 0.25 times the line frequency at power levels of 3kW and 0.5
times the line frequency at power levels of 300W.
RESULTS
In high voltage and current switching applications, the
saturation voltage VcEsa t can be a crucial design parameter.
Saturation voltage, and collector current play a major role in
determining the transistor losses. Figure 2 illustrates the
Collector-Emitter saturation voltage and its temperature
dependance. This test was conducted using the TEKTRONICS 371 high
power curve tracer. In accordance with the data sheets supplied,
VCE was measured at a forced Beta of i0, using IB=5A and Ic=50Hx
Under normal switch or inverter conditions, the major part
of the voltage drop across the transistor occurs in the
nonconductivity modulated region close to the N + layer. This
voltage drop is given by:
IcP epiwR
VzR" A
where wa=Wb-X o (W b- base width, x o- oxide thickness). The value
of internal base-collector voltage due to injection of the hole
concentration P(Wb) is given under high level injection by:
2
VBc-2V_in [ p (Wb) ]
n i
Assuming that the base has also entered the high injection level,
the base-emitter voltage is given as:
IcP epiW_
VcEsat"V_- V_c÷ A
and the total value of collector-emitter saturation voltage is
thus:
The temperature dependance of these equations can be shown by the
temperature dependance of the intrinsic carrier concentration,
ni, where:
ni- NT_-_ve- (EJ2kT)
the "effective" densities of conduction and valence band states
are:
2_mnkT ]3/2
Nc-2 [ h 2
Nv'2 [ 2_m;kT
h 2 ] 3/2
and the energy bandgap (EG=Ec-Ev) is:
(z T 2
EG(T) "EG(O)- T+----_
3
(in silicon EG(O) = 1.170eV, alpha = 4.73x10 -4, beta = 636)
The resistivity of the epitaxial layer:
1
P epi" q_=Nep i
where the electron and hole mobilities are determined using the
equations:
l.j,-88T_°'sT+
7.4xI08T -2"33
i+ [N/(i. 26X1017Tn 2.4) ] 0.88Tn °'146
M p-54.3 Tn 0"57+ i. 36 xlOBT -2"23
i+ [N/(2.35xI017Ta 2"4) ] 0.88Tn °'146
where Tn=T/300. Without using exact values for the B-E and C-E
junction hole and electron concentrations, and picking a
estimated figure of Ne-i=lO16cm -3 for the epitaxial doping level,
Table 3 demonstrates _e increase in VcEsa t with temperature. The
results calculated are similar to the measured data.
Table 3.
Temperature intrinsic carrier epitaxial delta
concentration n i resistivity VcEsat
(deq C) (cm -3) (ohm-cm) (V)
20 4.85xi09 0.4727 0.768
80 3.68xi011 0.6961 1.127
140 8.42xi012 0.9605 1.560
200 9.07xi013 1.2689 2.062
Figure 3 illustrates Collector-Emitter leakage current as a
function of temperature. This data was generated by applying a C-
E voltage with the HP6030A power supply, shorting the base and
emitter leads and reading the collector current with the
TEKTRONICS DM5120 programmable digital multimeter.
ICE is a measure of the reverse biased Collector-Base
leakage current. The equation for the reverse bias saturation
current in a p-n junction is shown below. It can be seen that the
4
intrinsic carrier concentration plays an important role in this
equation.
2 2
_.N m_pPnO] m N ni Dp n iIo-qA [ npo+ -qA [ LN NA +
_N
The approximate fractional change in the leakage current of
a reverse biased pn junction is given by:
1 ( alo 1 3 EG )IvR_coas:_t
•o
is approximately +8% per °C, or a doubling of leakage current for
every 12°C rise in junction temperature. Figure 3 shows the
increase in leakage current with temperature but with an initial
plateau. The flattening of the curve indicates saturation of a
junction in the device, most likely due to a fabrication process
in the device manufacture.
In the portion of the curve not effected by the saturation,
(IO0°C to 200°C) the leakage current was found to follow the
expected relationship. [IcE(150°C)=l.2xlO-4A ICE(200°C)=I.5xI0-3A
(l.5xlO -3 - 1.2xi0-2)/50Oc = 2.76xi0 -5 A/°C ]
The results of the Emitter-Base leakage current versus
temperature test are plotted Figure 4. This test also involves
the leakage current in a reverse bias p-n junction. The data was
generated by applying an emitter-base voltage using the PS5010
programmable power supply and measuring the leakage current using
the DM5120 programmable digital multimeter. The device again
demonstrated a saturation of leakage current in the lower
temperature range. An initial increase in the VEB=7V curve,
indicates the onset of E-B junction breakdown. And again the non-
saturated portion of the curve exhibits the leakage doubling
effect. [IcE(150°C)=I.3xlO-4A ICE(2OO°C)=2.3xlO-3A]
The DC current gain of the bipolar transistor was measured
using the TEKTRONICS 371 curve tracer at a constant VCE of 2.6V,
as per the device data sheet. Figure 3 shows a typical set of
curves for this test. These curves show the peak in Beta as the
generation and diffusion currents dominate the E-B junction, and
the Beta "fall-off" due to high level injection, Kirk effect
and or the series resistance of the base and collector.
Using simplified equations for the operation under the
normal "active region" bias, and considering the practical
situation were VBE>>Vt, we obtain the expression for dc current
gain:
5
w2 De
Table 4 shows the results of substituting estimated numbers
for doping levels (NAb=IO16cm-J, NDe=IO18cm-3), assuming comparable
values for emitter and base regions (We=Wb=lO-6m), then
calculating the electron and hole mobilities, and the diffusion
coefficients. The calculated values approximate the measured
results.
Leakage current testing on the MOSFET device included Gate-
Source leakage and Drain-Source leakage measurements. In both
Table 4.
Temperature mobility diffusion coeff. Beta
electron hole electron hole
(deq C) (cm2/sec) _cm2/sec)
20 246.3 467.5 6.222 11.810 52.7
80 232.8 325.8 7.084 9.914 71.5
140 218.4 241.5 7.779 8.598 90.5
200 203.7 187.6 8.305 7.649 108.6
[ I
cases, bias voltage was provided by the HP6030A power supply and
the current read by the DM5120 digital multimeter.
Analysis of the Gate-Source leakage data indicated currents
of less than lOnA (this data was lost in the noise resolution of
our equipment) at all temperatures for a gate-source voltage
range of +/-15V. This was deemed a negligible amount for any
practical circuit design.
Drain-Source leakage measurements versus temperature were
taken at gate-source voltages of OV and -5V. Figures 6 and 7 show
the results of the measurements. They exhibit the same doubling
o
of leakage current for every 12 C as the bipolar leakage
o 7 o 4
currents. [IDs(IO0 C)=IO- A, IDS(200 C)=4X10- A]
The attempt to reduce the drain-source leakage by applying a
negative gate-source voltage only reduced the current by a factor
of two over the entire temperature range. For the negative biased
gate-source data the drain-source voltage taken to a maximum of
40V to avoid exceeding the maximum rated drain-gate voltage.
The transfer characteristic curve of a MOSFET (I D vs VGS )
shows how the saturated drain current varies with applied gate-
source voltage for a constant value of drain-source voltage.
There are three distinct regions on the device's transfer curve.
In the region close to the VGS axis, a small amount of drain
6
current flows, but VGS is below the MOSFET threshold voltage VT
this is known as the sub-threshold region. In the region farthest
from the axis, the transfer curve becomes linear. This
linearization is the result of the effect known as "velocity
saturation". But the middle region is the most important. In this
region, the drain current is proportional to the square of the
difference between VGS and V T. Obviously a plot of ID I/2 versus
VGS in this region should be linear.
The data for the device's transfer curve was acquired from
the TEKTRONICS 371 curve tracer at a VDS of 5V. Figure 8 shows
the data plotted as ID I/2 VS VGS and the threshold voltage
interpolated as the straight line intercept of the ID=OA (VGs)
axis. Figure 9 depicts the calculated threshold voltages as a
function of temperature. Using the equation for the square law
region,
aID _ , 1 2 x aVr
-'_-''LDL_X'_ETX vGs-V_ aT ]
and the equation for the next region (velocity saturated),
aI_ CoxZ aver v avT
a---_"--_-- [ (VGS- VT) aT S_T--_ ]
The temperature dependance can be shown by:
F'-- kTln (NJni)
q
_ 4qNA "2 ,,÷ o
It can be shown that the derivative magnitude of the MOSFET
threshold voltage with respect to temperature is negative and
reasonably constant at about -3 to -6mV/°C. (Figure 9, slope of -
4.5mV/°C). The derivative of carrier mobility and saturation
velocity are also both negative, although VSA T is less sensitive
to temperature than the mobility.
The temperature dependance of the threshold voltage can also
be shown by the intrinsic carrier concentration and the doping
concentration reference voltage.
7
_F'- kTln [ND/ni]
q
_ 4qNA_VT'2_ F+ _ F
On-resistance (aDson) and RMS drain current determine both
the voltage drop and power loss in a MOSFET. There is a limit to
the minimum resistance of the channel. As the gate-body potential
is increase, more charge collects in the channel region. This
charge acts like an electrostatic shield to reduce the field in
the rest of the body. This action very closely resembles the
effect of space charge in a vacuum tube which acts to reduce the
electron emission from the cathode. In the MOSFET, the "space
charge" acts to limit the additional charge in the channel so
that the channel resistance quickly reaches it minimum.
Figure 10, On-Resistance Versus Temperature, was also
generated with data from the TEKTRONICS 371 curve tracer, using a
pulse I D of 75A and a constant VGs-VT of 6.5V.
Analysis of the Vos, based on the bulk-charge theory results
in:
v_s-vT vw 2 i/2_ vw
VDs-Vas-VT-Vw[( 2_F + (I+-_-_F) > (i+_) ]
With VGs-V 2 and ID=75A held constant, the doping concentration
reference voltage is the major contributor to the equation. As
shown above the reference voltage has a negative temperature
dependance, resulting in the increasing RDS shown in Figure i0.
CONCLUSION
Although further testing is necessary, circuit design for
elevated temperature utilizing both devices appears possible.
Leakage currents for both devices increased but not beyond a
usable range.
Future testing will include bipolar breakdown voltage and
switching and life-testing under load for both the MOSFET and
bipolar devices. Other devices to be investigated include the
MOS-controlled thyristor (MCT) and the insulated gate bipolar
transistor (IGBT).
8
Software
TEK EZ-TEST
TEK GURU II
MICROSOFT
Table I.
Description
GPIB TEST DEVELOPMENT SOFTWARE
FOR PERSONAL COMPUTERS
GPIB USER'S RESOURCE UTILITY
FOR THE IBM PERSONAL COMPUTER
QUICK BASIC
Device Name
TEK371
D2440
TKII401
HP6030A
AFG510
DM5120
DM5110A
DM5110B
PS5010A
PS5010B
DD9023
GPIB Primary address
1
2
4
5
7
8
16
17
22
23
27
Device
NPN
2N6023
N-MOSFET
RFH75N05E
MCT
MCTA60P60
Table 2.
Current
50A
75A
60A
Voltaqe
150V
50V
-600V
IGBT
TA9898 50A 500V
B]£(n
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ZO
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o_m I
JOZ
I
tC
t
L
tll
m
Z
@
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W
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Ir z
uJ
c
W •
I u
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IH L
wmI
I
°
m 11.
o _. tl
0_o
I
_ I -' >"
0 b.I :-.
o I _
• 0
0
I
Z 0.'
_- _o
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oO_ _ ___ _o_ ,_0 _mO
0 X 0
>.
m .j
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I- 0
3[
,,a iQl?- _ Om
., "¢--_H UJ I
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2 mu.,_
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ac i_ u
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1
Figure I. ORIGINAL PAGE IS
OF POOR QUALITY
1.0
0.9
0.8
0,7
_o 0"6
v
0,5
v_
_> 0.4
0.3
0.2
0.1
Collector.Emitter Saturation Voltage
NPN device _1 Ic=50A Ib=5A
50.0 100.0 150.0 200.0 250.0
Temperature (deg C)
Figure 2.
Collector-Emitter
I0 .... I ' ,
Current Versus Tempera%ure
Vbe = OV
' ' I ' ' ' ' I ' ' ' '
10 -aJ_
O
10 -6"0
10 -6"0 I i | | I I
0 50
I I , I | I I I
I00
Temperature (deg C)
, I
150 200
Figure 3.
rEmitter-Base Leakage Current
Iebo Versus Temperature
10-U .... , .... , .... , .... , ....
10 -4.0
q-
i0.__
O
[ 0-6.@
10 -V'O
0 5O 100 150
Temperature (deg C)
200 250
Figure 4.
150.0
DC Beta Versus Collector Current
, , , , * ,,| ' ' ' ' ' ' ''I
100.0
50.0
i i J , • = •i E = i I ! , , = i -"
10o.o 10 L°
Ic (_nps)
= _ i i ! i = ,
10 a°
Figure 5.
Drain-Source Leakage Current Versus Temperature
Vgs = OV (N-C_el Device #4)
10--S'O ..... i ' ' ' ' I .... !
10--_o
i0 -_
10 "e.°
10-7.o'x;I
10 -a'°
10 -g .0
I 1 I ! |
I00.0 150.0
Temperature (deg C)
I
200.0
Figure 6.
Drain-Source Leakage Current Versus Temperature
Vgs = -SV (N-Channel device #4)
10-ao
100.0 150.0
Temperature (deg C)
200.0
Figure 7.
4.0
Threshold Voltage Versus Temperature
N channel device #1 Vds-5V
' ' ' ' I ' ' '_ ' I ' ' ' ' I a , , , I ' ' ' '
:3.0
0
2.0
1.0
0.0
0.0
, , , , I , , , _ I , • _, , ! • , , ' I , , , ,
50.0 100.0 150.0 200.0 Z50.0
Temperature (deg C)
Figure 8.
Square Root of Id Versus Vgs
Threshold Voltage Interpolation (I_ channel device _1, Vds--SV)3.0 ......... i ......... , ....... i ......... , .......
4--
v
I*=-4
v
G¢
2.0
1.0
i_ ID D
_D
0 ,0, 0 "
0.0
0.0 1.0 2.0 3.0 4.0
v_ (v)
5.0
Figure 9.
0.020
On-Resistance Versus Temperature
N channel device #2 Vgs-Vt=constant Id=VSA
' ' ' ' I ' ' w , ! . , , , I ' ' ' ' I ' ' ' '
0.015
o 0.010
0.005
0 000 .... i .... I .... I .... t ....
0.0 50.0 I00.0 150.0 200.0 250.0
Temperature (deg C)
Figure i0.


Silicon device performance measurements to support temperature range enhancement

, /
/
SILICON DEVICE PERFORMANCE MEASUREMENTS
TO SUPPORT TEMPERATURE RANGE ENHANCEMENT
Cooperative Agreement NCC3-175
NASA
Lewis Research Center
Cleveland, Ohio
Semi-Annual Report
May 7, 1991 November 9, 1991
Prepared by:
James Bromstead
Bennett Weir
R. Wayne Johnson, Principal Investigator
Ray Askew, Principal Investigator
December 2, 1991
Auburn University
Center for the Commercial
Development of Space Power
231 Leach Center
Auburn, AL 36849
(NASF'-CR-I_;°522} .'_ILICO,_-_!I2EVICE OERFC}R_ANCE
;-_ASUP_,_CI'_TS TO 51JPP;2_T TZ_-!D_'_AT,j_F RAt_g-
( N_t,5;-_CLMCNT _e(_i _nnu,,_l R,aport, I M.sy - 9
_ov. i<)91 (Auburn Univ.) 35 t_ CSCL OgA
_,3/33
:\'_Z-142 9q
https://ntrs.nasa.gov/search.jsp?R=19920005077 2020-03-17T14:37:14+00:00Z
INTRODUCTION
This report details the efforts made since the last report was issued.
The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage
measurements have been analyzed. Switching measurement have been
made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796)
and the N-channel metal-oxide-semiconductor field effect transistor
(MOSFET) (RFH75N05E). Efforts have also been made to build an H-bridge
inverter. Also discussed in this report are the plans that have been made to
do life-testing on the devices, to build an inductive switching test circuit and
to build a dc/dc switched mode converter.
BJT BREAKDOWN VOLTAGE
Figure 1. shows the results from the BJT breakdown measurements.
Breakdown voltage in a power device is determined to a first order by the
doping concentration in the epitaxial layer and increases in the mean free
path. This relation is demonstrated by the equation below. The figure shows
an expected initial increase in breakdown voltage with temperature (about 5%
per 100°C), -with a sudden decrease in breakdown voltage after 150°C.
Where E is the permittivity of Si, Ebr is the critical breakdown field for the
doped Si and Nepi is the doping concentation.
This curve was typical of several BJTs (2N6032) tested. Analysis of this
phenomenon concluded increases in both the internal base resistance and
base-emitter leakage currents were creating an internal base emitter voltage
which begins to turn the device on. The breakdown voltage at 200°C is
approximately 10% below the value at 25°C and should not significantly
restrict designs at 200°C.
SWITCHING MEASUREMENTS
The major area of work since the last report has been switching tests
on the N-MOSFET, BJT and IGBT. Problems in drive circuitry and resistive
power loads have greatly delayed these tests.
As with the previous tests, only the heat sink mounted device was
placed in the test chamber. This configuration introduced large lead
inductances. Even with twisted pairs for the gate/base drive and supply/load
leads, ringing persisted in the output due to lead inductances. A major
concern was the reduction of these inductances to minimize the ringing.
The evolution of the switching test drive circuit is shown in Figure 2.
The first circuit was fabricated as a chip and wire hybrid and placed with the
device in the test chamber to reduce the drive lead inductances. This drive
circuit was later abandoned due to insufficient current from the totem pole
output to drive the MOSFET and IGBT. The next drive circuit tested uses the
IR2110 High Voltage MOSFET gate driver. This circuit proved the fastest
means of switching the N-MOSFET. The third circuit, although slower,
provided the higher current drive needed for the BJT and proved adequate
for the IGBT.
Problems persisted in the construction of a purely resistive load. In its
final form the load consisted of a parallel combination of 10 f_, 7 W
composite power resistors which were placed in the test chamber with the
device. This produced loads with a low temperature coefficient of resistance
(TCR), but sizable inductances (RL=0.67_ LL=0.121_H and RL=5.56 f_
LL=1.21_H as measured by an HP 4275A Multi-frequency LCR Meter at
10MHz).
Testing was performed by mounting the device and load in a Delta
Design 9023 test chamber. Twisted pair leads (<8 inch long) connected the
device to the gate/base drive circuit (driven by the Tektronics AFG5101
Arbitrary Function Generator) and the load to the voltage supply (HP6032
Power supply). Output waveforms were captured using a Tektronics 2440
oscilloscope, AM503 current amp with A6303 current probe and Tektronics
HC1000 color plotter, Figure 2A. Between each test the heat sink and device
were allowed to settle to the ambient chamber temperature. Tests were
preformed using 1001_sec pulses and a duty cycle of I second to avoid junction
heating
Figures 3-6 show typical N-MOSFET turn-off and turn-on waveforms
at 20°C and 200°C, for a Vr_3 = 30V, ID = 45A (Channel 1 - drain-source voltage
@5V/Div, Channel 2 - drain current @10A/Div). Ringing in the turn-off
voltage, Figures 3 and 5, waveforms was a result of natural oscillation
between the R, L of the load and the Cgd of the FET. A 25 _ gate resistor
reduced the ringing in the output, but increased rise and fall times. The graph
of switching time versus temperature, Figure 7, shows an almost fiat response
to temperature, but with switching time much higher than specified by the
manufacturer. The 0.67_ load used in the test has a time constant, tRL = 316ns,
which results in a 10-90% time of 694ns. This value contributed heavily to
our room temperature It)fall time of 620ns which is an order of magnitude
longer than the manufacturer's specified typical fall time of 17ns.
In addition to the RL time constant of the load, drive limitations of the
IR2110 and the charge-transfer characteristics of the RFH75N05E also
contribute to the slow switching times. As in most FETs the input impedance
of a power MOSFET consists of a high input resistance in parallel with an
equivalent input capacitance, consisting of the gate to source, Cgs, and the gate
to drain capacitance, Cgd. Due to the Miller effect on Cgd, the input
capacitance of the MOSFET is not well-defined. The effects of the change in
the input capadtance can be seen in the charge transfer characteristic of the
RFH75N05E MOSFET, Figure 8 [Harris Semiconductor RFH75N05E data
sheet], the normalized VGs voltages and corresponding VDS voltages for the
FET.
Each of the Vcs curves can be viewed as three separate regions of turn-
on or turn-off operation. In the first region of turn-on, the VGs curve is
linear, the gate voltage has risen to a level where there is drain current
conduction. During this period, the gate potential is in the pre-threshold
region, and charging the equivalent input capacitance, Cgd, thus the slope is
fairly constant. The rate of charging in this first region directly affects the
turn-on delay. In the second region, turn-on is complete when the drain
voltage has switched 90%. There is an abrupt increase in the input
capacitance, identified by the flattening of the gate-voltage curve. As the
MOSFET turns on, the Miller effect becomes more dominant. Cgd, and Cgs
being depletion-dependant are thus voltage-dependant and change rapidly in
this region. In the third region, since Cgd is depletion dependant, its
capacitance rises dramatically as the voltage between drain and gate
diminishes, and changes polarity when VDSdrops below V_s. As Cgd rises,
the Miller capacitance increaseseven more rapidly, despite the decrease in
voltage gain (dVDs/dVGs). The increasing Miller capacitance keeps the gate-
voltage characteristic nearly fiat until VSAT is reached. After the VDS voltage
has decayed to VSAT, the gate then resumes its rise to the imposed gate drive
level.
Figures 9-12 show typical BJT turn-off and turn on waveforms, for a
VCE = 30V and Ic - 45A. Again ringing in the turn-off voltage, Figures 9 and
11, is due to the inductive load. The maximum specified rise time for the
2N6032 is l_s and the maximum specified fall time is also l_ts. The values
measured at 20°C, VCE rise time of 180ns and a VCE fall time of 120ns,
fall well within the maximums specified by the manufacturer. A graph of the
change in switching times for the BJT, Figure 13, indicates a fairly fiat
response in the turn-off voltage and the turn-on current. Most notable in the
figure is a 5.59 ns/°C increase in the BJT turn-off current and turn on voltage
times. This rate of increase is noted in the turn-off current after 150°C.
Figures 14-17 show the IGBT turn-off and turn-on waveforms at 20°C
and 200°C, for a VDS = 150V, Ic = 30A. Ringing in the turn-off voltage
waveforms is again a result of the inductive load. A rise time of 250ns and a
fall time of 1.214_ts were measured for Vc_ at 20°C. The measured fall time is
less than the specified typical value of 1.8_s. The time constant for the 5.56_
load used is 0.218bts which results in a 10-90% time of 0.479_s. This indicates
that the load and temperature do not contribute to the measured times, as
shown in Figure 18.
Figures 7, 13 and 18 show a graphical representation of the rise and fall
times for the devices. These graphs show a fairly fiat response of switching
time over the 20°C to 200°C operating temperature. Because the rise and fall
times were relatively unaffected by temperature in this switching test it can be
seen that all the devices tested still switched at useful speeds even at 200°C.
H-BRIDGE CONVERTER
As part of the lifetime testing, an H-Bridge converter has been designed
and built, Figures 19 and 20. With an operating frequency of ~21.5kHz and
parallel resonant load, the inverter offered a design in which both the N-
MOSFET and IGBT could be used as the switching elements. A problem
encountered in the testing the MOSFET version of the inverter has been
feedback between the H-Bridge and the gate driver circuitry.
"Hard" driving of the high-side transistors caused coupling of the high
voltage power supply with the driver power supply through the same "Miller
effect" capacitance found in the MOSFET switching tests. This coupling
resulted in ringing on the +15V line. The ringing in the +15V supply line
created changes in the UC3860's VREF and IVFo , resulting in changes in the
frequency and width of the UC3860's alternating drive pulses. This led to
failures in the IR2110 high-side drivers. Increasing the bypass capacitance on
the +15V line did not help with the oscillation. As a solution to this problem
the voltage supplies of the UC3860 and IR2110s have been separated.
Reducing the IR2110 supply to +14V has also helped to reduce ringing in the
gate drive.
Figures 21-24 show operating waveforms of the MOSFET inverter at
20°C. Figures 21 and 22 show the drain-source voltage ,VDs, (Channel 1-
20V/Div) and gate-source voltage ,VGs, (Channel 2 -10V/Div) of M3, a low-
side device, and M4, a high-side device, respectively. Due to the limitation in
rated drain-source voltage of the RFH75N05E to 50V, (M4 -45V), the peak
VDS limited the operation of the inverter to a peak device drain current ,ID,
of 5.8A. Reduction in the load resistance will allow operation at increased
current by reducing the load voltage. The VDS and ID, of the low-side device
M3 are shown in Figure 23, (Channel 1- 20V/Div, Channel 2- 2A/Div), note
the commutation of current through the MOSFETs body diode. In our
configuration, the natural frequency of the RLC load can be seen to be higher
than the inverter switching frequency, thus the diode current should be
commutated by the companion FET in the totem pole. But due to the split
inductor configuration, the diode current is commutated in the opposing part
of the totem pole, and diode recovery problems at higher current will occur.
Detail of the forward conduction of the body diode is shown in Figure 24. To
remedy the commutation problem the circuit is being reconfigured with a
Schottky diode (MBR3535) added in series with each FET and a fast recovery
diode (1N3891) in parallel with each FET/Schottky combination as the free-
wheeling diode. Reverse current now will then flow through the fast
recovery diode, and because of the fast reverse recovery nature of the diode,
the current during recovery will be reduced. In the IGBT version of the
inverter, the free-wheeling diode is also necessary.
FUTURE PLANS
Life-Testing
Life-testing will be accomplished by running the devices in the
configuration detailed in the section on the H-bridge inverter. An inductive
switching test will also be performed on the devices. A test circuit will be
designed.
Failure Analysis
Failure analysis has begun with N-MOSFET that failed under testing,
Figure 25. This device no longer responsed to gate drive and produces a
resistive I-V characteristic on the curve tracer. It is thought that the source
metalization has "punched through" to the drain. After the passivation layer
of SiO2 and source aluminum have been etched and the source-channel will
be Argon sputter-etched in an Auger system to profile the elemental content
of the junction.
DC/DC Switch Mode Converter
Plans have been made to design a dc/dc switched mode converter.
Figure 26. shows the flyback converter configuration which has been selected
as the basic converter topology. The design will be implemented using
IGBT's and will convert 18V to 120V at a power level of 100W.
Thick film hybrid technology will be used to construct the control
circuitry. The materials used in thick films are processed in excess of 800°C
and are very stable at 200°C. LM555's are currently being considered for use in
the control circuit and will soon be characterized at elevated temperatures.
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Silicon device performance measurements to support temperature range enhancement

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