Signalling over long interconnect is a dominant issue in electronic chip design in current technologies, with the device sizes getting smaller and smaller and the circuits becoming ever larger. Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced closer and closer together and signal rise and fall times go into the sub-nano second region, the coupling between interconnects assumes great significance. The resulting crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. In this paper we attempt to quantify the effect of worst-case capacitive crosstalk in parallel buses and look at how it affects repeater insertion in particular. We develop analytic expressions for the delay, buffer size and number that are suitable in a-priori timing analyses and signal integrity estimations. All equations are checked against a dynamic circuit simulator (SPECTRE

Pamunuwa, Dinesh B.

Tenhunen, Hannu

English

Lancaster E-Prints

Repeater Insertion To Minimise Delay in Coupled Interconnects 
Dinesh Pamunuwa and Hannu Tenhunen 
ESD Lab, Department of Electronics, Royal Institute of Technology 
Electrum 229, Isafjordsgatan 22-26, SE-I 64 40 Kista, Sweden 
dineshIhannu@ele.kth.se 
ABSTRACT 
Signalling over long interconnect is a dominant issue in 
electronic chip design in current technologies, with the 
device sizes getting smaller and smaller and the circuits 
becoming ever larger. Repeater insertion is a well estab- 
lished technique to minimise the propagation delay over 
long resistive interconnect. In deep sub-micron technolo- 
gies, as the wires are spaced closer and closer together and 
signal rise and fall times go into the sub-nano second 
region, the coupling between interconnects assumes great 
significance. The resulting cross talk has implications on 
the data throughput and on signal integrity. Depending on 
the data correlation on the coupled lines, the delay can 
either decrease or increase. In this paper we attempt to 
quantify the effect of worst-case capacitive cross talk in 
parallel buses and look at how it affects repeater insertion 
in particular. We develop analytic expressions for the 
delay, buffer size and number that are suitable in a-priori 
timing analyses and signal integrity estimations. All equa- 
tions are checked against a dynamic circuit simulator 
(SPECTRE). 
1. INTRODUCTION 
Signal Propagation on long resistive interconnect lines 
is a function of the product of the line resistance and 
capacitance, commonly known as the RC delay. Since 
both the resistance and capacitance show a linear increase 
R 
with length, the delay increases quadratically with length. 
Because the prophecy of Moore’s law in VLSI circuits has 
held true over the years, interconnections have become 
smaller in cross-section and longer in length with each 
succeeding generation of CMOS technology. Hence there 
has been a lot of investigation into the problem of repeater 
insertion in long interconnect. Bakoglu [ 11 presented an 
analysis based on characterizing the repeater with an input 
capacitance and an output resistance which was one of the 
pioneering works in this area. Wu and Shiau in [2]  
improve on the repeater model and use a linearised form 
of the Schichmann-Hodges equations while Adler and 
Friedman in [3] use Sakurai’s alpha power model to 
include the effect of velocity saturation in short channel 
devices. Ismail and Friedman in [4] present an analysis 
which models inductance in the interconnect for the first 
time. Some other work on repeater insertion is given in [5] 
and [ 61. 
In the future generation of VLSI circuits when the fea- 
ture size shrinks to a fraction of a micro meter, and more 
and more transistors are placed on a single chip, cross talk 
will pose a serious challenge in designing VLSI systems. 
In closely coupled interconnects such as in long parallel 
buses, cross talk can result in speeding up of the signal or 
cause considerable additional delay- depending on the 
correlation between the data on the different lines. We 
present in this paper an analysis for repeater insertion to 
minimise delay in parallel coupled interconnects with 
0-7695-0831-6/00 $10.00 0 2000 IEEE 
~~ 
- - 
Figure 1. Configuration for investigating effect of cross talk 
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worst-case capacitive cross talk. Our methodology uses 
the same repeater model as in [l] and incorporates cou- 
pling capacitance between adjacent interconnect lines. The 
equations we derive reduce to Bakoglu's equations when 
the coupling capacitance term is set to zero, and are suita- 
ble in a-priori signalling estimates. 
1000 
2. DELAY MODEL FOR COUPLED 
INTERCONNECTS 
100 100 97920 98000 -0.08% 
The first step in analysing the effect of cross talk on 
repeater insertion is to have an accurate delay estimate for 
the step response. From now on, whenever delay is men- 
tioned we are always talking about the 50% delay, since 
this corresponds to the delay of the output to the switching 
threshold of an inverter. We consider a line with coupling 
on two sides and derive a model for the step response with 
worst case coupling: that is both aggressor lines switch in 
a direction opposite that of the victim line. The configura- 
tion for this analysis is shown in Fig. 1 .  
V d K  
7 
- 
- - 
Figure 2. Lumped model with cross talk 
The .reasoning behind the derivation of the model 
requires a short diversion into previous work. The delay of 
a lumped RC circuit is analytically solvable and is 
The step response of a distributed RC circuit has no 
closed form time domain solution. However a closed form 
frequency domain solution exists, and it is possible to 
make an approximation for b>RC and t<<RC and use 
these equations to separately calculate the low frequency 
and high frequency portions of the output waveform (Ref. 
[I]). This leads to the following delay model for the step 
response to a distributed RC line: 
' 0 . 5 ,  disrr = 0.4RC ( 2 )  
Now the step response for a a lumped RC circuit with 
coupling as shown in Fig. 2 is given by: 
I f 
(3) 
Just as the delay for the distributed line can be approxi- 
mated by To,5 = h * RC where RC is the time constant in 
the lumped model, and h a constant, We have approxi- 
mated the delay for the distributed lline with cross talk by a 
model given by: To.s = h, * RC,r + hb * R(2C,+C,r) where 
RC, and R(2C,+C,r) are the two time constants present in 
the lumped model. If there is an additional line acting as 
the aggressor, the coupling capacitance term doubles. For 
a distributed line with two aggressor nets as shown in Fig. 
1, this reduces to the following equation:. 
'OS, disrr, wirhCT = 0.4RCs + 0.58 R C c  (4) 
Table 1. Comparison of actual delay and delay predicted 
by model for a distributed RC line with cross talk 
10 1 1  I100 I640 I 580 I 8.33% I 
980 -0.09% 
1000 980 980 -0. I % 
1000 I 1 I 10 I 6560  I 6200 I 5.5% I 
38620 
1000 1 100 I 10 I 45090 I 45800 I -1.58% I 
The constants were obtained by running simulations for 
a range of R, C, and C, and then fitting the above model to 
the data. Note that when C, is set to zero, this reduces to 
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Bakoglu's approximation given in Eq. (2). Eq. ( 4 )  is 
appropriate for on-chip lines which are typically very 
lossy and the inductance is negligible. Ref. [7] gives 
closed form equations for the approximate coupling noise 
in the time domain, for coupled lines where the resistance 
is small compared to the inductive impedance. 
Given in Table 1 are the actual delay values as obtained 
from simulations and the values predicted by the model in 
Eq. (4) .  It is seen that there is good agreement for a wide 
range of R, C, and C, parameters, and that the correlation 
is weakest when C, > lOOC,, which is an unrealistic sce- 
nario in an actual situation. For all practical purposes, this 
model is as accurate as the very commonly used approxi- 
mation for a distributed line as given in Eq. (2), which is 
reported to exhibit an accuracy of within 4% for a wide 
range. This delay model is used in the next section to 
obtain equations for repeater numbering and sizing for 
minimum delay. 
R (ohm) Cs (fF) 
1000 1000 
3. REPEATER INSERTION 
Cc (fF) Error Percentage 
1000 4.6% 
To reduce delay the long lines in Fig. 1 are broken up 
into shorter sections, with a repeater (an inverter) driving 
each section. Let the number of repeaters including the 
original driver be k, and the size of each repeater be h 
times a minimum sized inverter. The output impedance of 
a minimum sized inverter for the particular technology is 
R ,  and the output capacitance C,, Then the output 
impedance of an h sized driver becomes R,@, and the 
output capacitance h *e, This configuration is sketched 
out in Fig. 3, where the symbol refers to a capaci- 
tively coupled interconnect as shown in Fig. 1. Now with 
reference to Fig. 3 and using superposition with the delay 
Eqs. (1,2 and 4 )  the total delay becomes: 
1000 
1000 
( 5 )  
100 100 3.2% 
IO0 1000 2.7% 
It is assumed that the load C, is equal to the input 
capacitance of an h sized inverter. This delay expression 
follows the Bakoglu model, and the difference is in the 
terms in bold, which are the result of modelling the cross 
talk in the delay. The coefficient of 2.2 for the lumped term 
involving the coupling capacitance C, is to take the Miller 
effect into account. The accuracy of this approximation for 
100 
100 
the delay of a section can be checked using table 2, which 
shows the difference between the predicted delay and the 
delay as given by SPECTRE simulations. Results are 
given for a range of values which are deemed to be rele- 
vant. The error is contained to within 5% over the full 
range of test values, of which only a sample is given here. 
10 100 -2.3% 
10 10 2.2% 
I I 1000 I 1000 I 100 I -1.1% 
I I 100 I 100 I 10 I -2.1% 
Now to find the optimum h and k for minimising delay, 
the partial derivatives of Eq. (5)  with respect to k and h are 
equated to zero. Setting 
= o  at0.5 - 
a k  
leads to 
= $ .4RCs+Q.58RC,  (6)  
o.7 Rdrv Cdrv 
Similarly 
leads to 
Note that when the coupling capacitance term C, is set 
to zero, Eqs. (6 and 7) simplify to the Bakoglu equations. 
Given in Table 3 is a comparison of the buffer sizes, 
number and delay as given by the Bakoglu equations and 
the equations taking cross talk into account for a number 
of line resistances and capacitances. Obviously, the differ- 
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Table 3. Investigation of the effect of including cross talk in buffer sizing and numbering 
R 
(ohm) 
100 
100 
100 
100 
lo00 
lo00 
lo00 
1000 
c s  
(PF) 
0.5 
0.5 
1 
1 
0.5 
0.5 
k l  hl 
(;,!$ I (without I (without 
cross talk) cross talk) 
I I 
0.5 I 0.6 I 79 
0.8 112 
0.5 I 1.9 I 25 
1 I 1.9 I 25 
k2 (with 
cross talk) 
0.9 
1.2 
1.2 
1.3 
3 
3.7 
3.5 
4.2 
ence in the delay times increases with increasing coupling 
capacitance. In certain cases the difference is as much as 
50%. Critical nets which are buffered without taking 
cross-talk into account will exceed the timing slack. It 
should be noted that the optimal sizes taking cross talk 
into account are considerably higher than those given by 
the Bakoglu equations. Setting C, = CJ2 in all of the 
above will result in the equations corresponding to a sys- 
tem with a single aggressor.We ran Spectre simulations on 
an actual 0.35 micro meter AMs technology and com- 
pared the impact of the different buffer numbering and siz- 
ing to further verify the model. The average output 
impedance of a minimum sized inverter in that technology 
is 10k ohm while the input capacitance is approximately 
10f F. In Table 4 are given the results of simulations run 
for two nets, the first 1 cm long and the second 3 cm long 
where parallel nets switch in the opposite direction as in 
Fig. 1. Both lines are 0.7 pm wide and 0.5 pm thick with a 
spacing between the lines of 0.7 pm and a dielectric thick- 
ness of 0.5 pm. The resistive and capacitive parasitics 
were obtained from typical per unit length values. The 
buffers were numbered and sized according to Bakoglu’s 
equations (k ,  and h,) and according to the cross-talk analy- 
sis model (k,  and h,) with k being rounded to the nearest 
integer. The delay in both cases was calculated using the 
new metric proposed in Eq. (5). The rise times of the sig- 
h2 (with 1 Td,, (using I Td,, (using I ~~s~~~~ I 
cross talk) kl & hl)  (ns) k2 & h2) (ns) disregarding 
I 1 
184 I 0.39 I 
I I 
248 0.62 
260 I 0.56 I 0.45 I 25% I 
1.25 I 0.98 I 28% I 58 I 
78 I 2.02 I 1.30 I 56% I ;; I :::; I 1.11 1 11% 1 
1.39 27% 
nals in all cases were set to 100 ps. It can be seen that there 
is good agreement with the model. 
The effect of cross-talk on delay can also be seen in the 
eye diagrams shown in Fig. 4. Since the eye diagrams are 
obtained by simulating with pulse streams instead of sin- 
gle steps, the eye opening is a statistical measure of delay. 
These were obtained with different pseudo-random bit 
streams running on the three lines, with a bit frequency of 
lGHz and rise and fall times of IOOp seconds. The simula- 
tions were carried out for the 3 cm line with parameters as 
given in table 4. The first diagram is with repeaters num- 
bered and sized according to k, ancl h, and the second with 
repeaters sized and numbered according to k, and h, as 
given in table 4. The first has an eye opening as shown, 
while in the second this has completely closed. 
4. SUMMARY 
We have presented a worst case delay model for parallel 
coupled interconnects and shown that it is accurate to 
within 95% over a wide range of parameters. We have 
used this model to study the impact of cross talk on buffer 
sizing for delay minimisation in long nets, and derived a 
new set of equations that give the: number and optimum 
size of the repeaters. The delay equation for a single sec- 
tion of the line was verified with simulations and found to 
Table 4. Comparison with simulations run in a 0.35 pm technology 
Td,, with Spectre 
Simulations (ns) I Cross-talk Sizing I Net length Error 
Bakoglu Cross-talk 
Sizing Sizing 
7.1% 
4.3% 4.7% 
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-: VT ”/net1688”) 
4.5 x: VT{”/netl 144“) c 
-1.0 
3.0 
2.0 
1.0 
0.5 
I Eye opening 
. .  . . . . . . . . I . .  . . . . . . . I 
4.0 
3.0 
2.0 
1.0 
0.0 
-1.0 
e 
-: VT ”/net1620” 
x :  VT{“/netl144”] 
F 
. . . . . . . . . . . . . . . . . . . . .  
0.5 2.0n 
Figure 4: Eye diagrams for different repeater configurations for a 3cm long net with cross talk 
be accurate to within 95% over the range of test parame- 
ters, which were chosen to encompass a wide spectrum. 
Finally we tested our delay model and the buffer sizing 
equations by running Spectre simulations with transistors 
from an actual 0.35 micrometer AMS process. We 
obtained an accuracy of around 85% for the specific cases 
investigated. Also we show by means of the eye diagram 
at the output of the line, that disregarding cross-talk can 
result in closure of the sampling window. 
All the equations derived in this paper are completely 
general and are in no way restricted to a particular technol- 
ogy. There is a representative value for different regions so 
to speak, defined by the R, C, and C, coordinates. Typical 
values for a wide range of buses in VLSI circuits are thus- 
represented. 
Even in modem synthesis programs, the capability of 
the routing tool to take into account effects such as cross 
talk is very limited. This results in poor layout and 
repeated iterations of the design cycle. The availability of 
closed form equations to predict the timing behaviour in 
the face of cross talk would hence potentially be very use- 
ful. 
5. REFERENCES 
[ 11 Bakoglu H. B., “Circuits, Interconnections, and Pack- 
aging for VLSI”, Addison Wesley 1990. 
[2] Wu C. Y. and Shiau M., “Accurate speed improvement 
techniques for RC line and tree interconnections in 
CMOS VLSI”, in proc. IEEE International Symposium 
on Circuits and Systems (ISCAS) 1990, pp. 2.1648- 
2.165 1. 
[3] Adler V. and Friedman E. B., “Repeater Design to 
Reduce Delay and Power in Resistive Interconnect”, in 
IEEE Transactions on Circuits and Systems-11, Analog 
and Digital Signal Processing, Vol. 45, No. 5 ,  May 
1998 
[4] Ismail Y. I., and Friedman E. G., Effects of Inductance 
on the Propagation Delay and Repeater Insertion in 
VLSI Circuits, IEEE Transactions on VLSI Systems, 
April 2000, vol. 8, pp. 195-206 
[5] Nekili M. and Savaria Y., “Optimal methods of Driving 
Interconnections in VLSI Circuits”, in proc. IEEE 
International Symposium on Circuits and Systems 
(ISCAS) May1992, pp. 21-23. 
Driving Long Uniform Lines”, IEEE J. Solid State Cir- 
cuits, vol. 26, pp. 32-40, Jan. 1991. 
[7] Tang K. T. and Friedman E. B., “Peak Crosstalk Noise 
Estimation in CMOS VLSI Circuits”, in proc. IEEE 
International Symposium on Circuits and Systems 
[6] Dar S, Franklin M. A., “Optimum Buffer Circuits for 
(ISCAS) 1999 vol. 1, pp. 541-544 
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Repeater insertion to minimise delay in coupled interconnects.

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