Hardware customization for scientific applications has shown a big potential for reducing power consumption and increasing performance. In particular, the automatic generation of ISA extensions for General-Purpose Processors (GPPs) to accelerate domain-specific applications is an active field of research to accelerate. Those domain-specific accelerated processors are mostly evaluated in simulation environments
due to technical and programmability issues while using real hardware. There is no automatic mechanism to test those custom units in a real hardware environment. In this paper we present a toolchain that can automatically identify candidate parts of the code suitable for reconfigurable hardware
acceleration. We validate our toolchain using ClustalW.Postprint (published version

Gaydadjiev, Georgi

González, Cecilia

Jiménez González, Daniel

Martorell Bofill, Xavier

Álvarez Martínez, Carlos

English

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Fast Evaluation Methodology for Automatic CustomHardware PrototypingCecilia Gonza´lez∗, Daniel Jime´nez-Gonza´lez†, Xavier Martorell∗, Carlos ´Alvarez† and Georgi Gaydadjiev‡∗Barcelona Supercomputing Center †Universitat Politecnica de Catalunya ‡Technical University of Delft{cecilia.gonzalez,xavier.martorell}@bsc.es {djimenez,calvarez}@ac.upc.edu g.n.gaydadjiev@tudelft.nlI. INTRODUCTIONHardware customization for scientific applications hasshown a big potential for reducing power consumption andincreasing performance. In particular, the automatic generationof ISA extensions for General-Purpose Processors (GPPs) toaccelerate domain-specific applications is an active field of re-search to accelerate [1], [2]. Those domain-specific acceleratedprocessors are mostly evaluated in simulation environmentsdue to technical and programmability issues while using realhardware. There is no automatic mechanism to test thosecustom units in a real hardware environment. In this paperwe present a toolchain that can automatically identify can-didate parts of the code suitable for reconfigurable hardwareacceleration. We validate our toolchain using ClustalW.II. AUTOMATIC PROTOTYPING AND EVALUATIONThe main objective of our work is to provide an automatedtoolchain for the generation and evaluation of a domain-specific processor architecture. The diagram of this architec-ture is shown in Figure 1.Fig. 1. The target domain-specific architecture.The targeted architecture is composed of a fixed ISAcomputing unit, which is extended with new ISA instruc-tions mapped on the reconfigurable unit that implementsand executes those extensions. The extensions are translatedinto hardware descriptions and mapped in the customizablearea of the processor, through reconfiguration technologies.Additionally, there may be a flexible Scratchpad Memory(SPM) connected directly to the main memory of the systemthrough DMA transfers.The main drawback of testing such architecture is that, forthe best of our knowledge, there is not a fast prototypingplatform. In this paper, we present our current work on anautomatic toolchain to generate specific units for a domain ofapplications with fast testing.In Figure 2 we show an outline of the main parts that makeup the process of prototyping. In steps 1, 2 and 3, we identifythe new ISA extensions for our domain-specific processor.In steps 4 and 5 we generate, respectively, the necessaryhardware and binary code to use those new extensions in ourapplications. The description of the exact steps is as follows:Fig. 2. Outline of the automated process of prototype generation.A. Customization: ISA extensions detection1) Profiling. The source code of the application is profiledto obtain the frequency of execution of every codesection.2) Candidates identification. The application is repre-sented as the Data Flow Graph (DFG) of the sequenceof instructions. The DFG is examined at the basicblock level to get subgraphs of basic instructions thatmeet architectural constraints, e.g. the number of inputsand outputs or the kind of instruction. Each of thoseidentified subgraphs is a candidate as a customizedinstruction.3) Selection of ISA extensions. The final selection is doneusing a greedy algorithm. The search is guided by afunction that uses the information extracted during theprofiling. This function tries to maximize the gain ofthe new instruction proposed, depending on the metricthat has been chosen. The maximum number of newinstructions that are selected is limited by the areaavailable in the reconfigurable hardware.B. Hardware and code generation4) Generation of the hardware description. Once eachnew instruction is selected, its hardware description isgenerated. The new unit is placed into the reconfigurablearea of the processor, as shown in Figure 1.5) Code generation. The compiler for the target archi-tecture is parametrized to detect the code patterns thatmatch the new instructions. Then, the compiler generatesthe code using the new ISA extensions.III. CURRENT IMPLEMENTATIONThe prototyping and evaluation platform for our currentimplementation is MOLEN [3]. MOLEN is a polymorphicprocessor composed of two main components: a core pro-cessor, that performs tasks like a GPP, and a reconfigurableprocessor with a Custom Computing Unit (CCU), that runsas a coprocessor. In the MOLEN programming paradigm,applications run mainly on the GPP. However, some parts areimplemented in the reconfigurable hardware of the CCU tospeed-up the overall application.Profiling and identification of candidates, steps 1 and 2in Figure 2 respectively, have been implemented within theTrimaran framework [4]. Selection of ISA extensions (step 3),is a standalone program in the toolchain with different guidingfunctions for the selection of the new instructions.The hardware description generation (step 4) is done usingthe DWARV toolset [5], which is a C to VHDL translatorspecific for MOLEN. It translates the functions preceded bythe to dfg pragma directive to VHDL that can be integrated inthe MOLEN platform. For instance, in order to customize theMOLEN platform to accelerate the source code of the programin Figure 3.a, we automatically generate the code shown inFigure 3.b. Therefore, for each selected new instruction, wegenerate a function equivalent with the source code lines thatinclude the new instruction, annotated to be transformed intothe hardware description of a CCU.The code generation (step 5 in the Figure 2) is done usingthe compiler that targets MOLEN. That compiler identifiesthe pieces of code that are going to run on the reconfigurablearea with the call fpga pragma directive and generates theinstructions needed to start the execution of the CCU. Wefeed the MOLEN compiler with a C code that has beenautomatically modified with pragmas and calls to the CCUsequivalent to the new instructions (see Figure 3.c).a) original_source_code_line/* Including the new instruction */b) #pragma to_dfgint funct_example(int param_example){ original_source_code_line }...funct_example(param);c) #pragma call_fpga CCU_funct_exampleint CCU_funct_example(int param_example){ original_source_code_line }...funct_example(param);Fig. 3. (a) Original code. (b) Code for DWARV toolset. (c) Code for MOLENcompiler.We have tested our toolchain with a bioinformatic appli-cation, ClustalW, that is a sequence alignment program. TheMOLEN processor has been deployed on a XUP with a FPGAVirtex II Pro. Figure 4 shows the speed-up that every singleCCU detected can achieve compared to its software equivalentrunning on the PowerPC embedded in the FPGA Virtex II Pro.As it can be seen, a single CCU can achieve up to 8.53x ofspeed-up. When the best subset of those new instructions isused the overall application achieves a speed-up of 2.15x.Fig. 4. Speed-up per CCU compared to the software version. The x-axisshows CCU identifiers.IV. CONCLUSIONS AND FUTURE WORKThis work presents a preliminary toolchain to automaticallygenerate hardware prototypes and test them. Initial resultsprove that our framework delivers an speed-up over 2x forthe tested application on the MOLEN platform. To overcomethe limitations of our current implementation, we are changingthe prototyping platform to a new one based on OpenSPARCT1 processor. That processor has coprocessor hardware andISA support. However, Trimaran does not target SPARC.Therefore, we are porting our ISA detection algorithms to theLLVM compiler infrastructure, since it can generate SPARCobject files.ACKNOWLEDGMENTSWe would like to thank Yana Yankova from TU Delft forher support using the DWARV toolset and Pan Yu from theNU of Singapore for his help with the extensions to Trimaran.The researchers at BSC-UPC were supported by the SpanishMinistry of Science and Innovation (no. TIN2007-60625,CSD2007-00050 and TIN2006-27664-E), the European Com-mission in the context of the SARC project (no. 27648), theHiPEAC Network of Excellence (no. IST-004408), and theXilinx University Program.REFERENCES[1] Diviya Jain, Anshul Kumar, Laura Pozzi, and Paolo Ienne, “AutomaticallyCustomising VLIW Architectures with Coarse Grained Application-specific Functional Units,” in Proceedings of the 8th InternationalWorkshop on Software and Compilers for Embedded Systems, 2004.[2] Nathan T. Clark and Hongtao Zhong, “Automated custom instructiongeneration for domain-specific processor acceleration,” IEEE Trans.Comput., vol. 54, no. 10, pp. 1258–1270, 2005, Member-Scott A. Mahlke.[3] S. Vassiliadis, S. Wong, G. N. Gaydadjiev, K.L.M. Bertels, G.K. Kuz-manov, and E. Moscu Panainte, “The molen polymorphic processor,”IEEE Transactions on Computers, pp. 1363– 1375, November 2004.[4] “Trimaran: An infrastructure for research in backend compilation andarchitecture exploration,” http://www.trimaran.org, August 2008.[5] Y. D. Yankova, G.K. Kuzmanov, K.L.M. Bertels, G. N. Gaydadjiev, Y. Lu,and S. Vassiliadis, “Dwarv: Delftworkbench automated reconfigurablevhdl generator,” in In Proceedings of the 17th International Conferenceon Field Programmable Logic and Applications (FPL07), August 2007,pp. 697–701.

Fast evaluation methodology for automatic custom hardware prototyping

Hardware customization for scientific applications has shown a big potential for reducing power consumption and increasing performance. In particular, the automatic generation of ISA extensions for General-Purpose Processors (GPPs) to accelerate domain-specific applications is an active field of research to accelerate. Those domain-specific accelerated processors are mostly evaluated in simulation environments

due to technical and programmability issues while using real hardware. There is no automatic mechanism to test those custom units in a real hardware environment. In this paper we present a toolchain that can automatically identify candidate parts of the code suitable for reconfigurable hardware

acceleration. We validate our toolchain using ClustalW

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Fast evaluation methodology for automatic custom hardware prototyping

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