在fPgA的设计过程中,调试与仿真工作需要耗费大量时间。利用C语言相对VErIlOg语言在过程控制方面具有优势,采取系统C模型通过PlI接口给VErIlOg模型产生测试矢量,降低了设计仿真工作的复杂度。但是由于当今的VErIlOg仿真器速度慢,难以满足大数据量和高实时性的仿真要求。通过将设计中验证通过的VErIlOg模型在fPgA中实现并与PC机通过通信接口实现数据交互,待验证的VErIlOg模型运行在VErIlOg仿真器上,构成软硬件协同仿真加速系统,克服了软件仿真慢的特点而实现实时仿真,从而极大的加快了设计的仿真速度。During FPGA design,it is very difficult to debugger and simulation for complex hardware circuit design.Because using C language in process control is more superior than Verilog language,the method that system C model generate test signals to Verilog model by PLI interface,will be carried out.It reduces the complexity of design and simulation.However,nowadays Verilog simulators are too slow to fit the requirement,which demands large system data and high real time simulation.So,if Verilog model runs in FPGA,and communicates with C model running on the PC,constituting the software and hardware co-simulation acceleration system.The system will overcome the tardiness of soft simulation and achieve real time simulation.Besides,it greatly speed up the simulation of system
