textThe management of power consumption while simultaneously delivering
acceptable levels of performance is becoming a critical task in highperformance,
general-purpose micro-architectures. Nearly a third of the energy
consumed in these processors can be attributed to the dynamic scheduling
hardware that identifies multiple instructions to issue in parallel. The energy
consumption of this complex logic structure is projected to grow dramatically
in future wide-issue processors.
This research develops a novel Hybrid-Scheduling approach that synergistically
combines the advantages of compile-time instruction scheduling and
dynamic scheduling to reduce energy consumption in the dynamic issue hardware.
This approach is predicated on the key observation that all instructions
and all basic-blocks in a program are not equal; some blocks are inherently
easy to schedule at compile-time, whereas others are not. In this scheme,
programs are thus partitioned into low power “static regions” and high power
“dynamic regions”. Static regions are regions of the program for which the
compiler can generate schedules comparable to the dynamic schedules created
by the run-time hardware. These regions bypass the dynamic issue units and
execute on specially designed low-power, low-complexity hardware.
An extensive evaluation of the proposed scheme reveals that the HybridScheduling
approach wherein instructions are routed to a scheduling engine
tuned to a region’s characteristics can provide substantial reduction in processor
energy consumption while concurrently preserving high levels of performance.Electrical and Computer Engineerin
