textImprovements in the integrated circuit performance over the past three
decades have been mainly possible by the downward scaling of device
dimensions. Device scaling requires that all lateral and vertical dimensions of the
transistor be scaled. In the last decade, in order to continue conventional scaling
of the source/drain junctions, the semiconductor industry has relied heavily on
decreasing the implant energy, and also on minimizing the thermal budget of the
activation anneal. With Transient Enhanced Diffusion less pronounced for low
implant energies and sharper anneal temperature profiles, interactions of dopant
atoms and point defects with surface films and interfaces are becoming of
paramount importance in determining the concentrations of dopants and point
defects, and therefore the resulting device structures. A nitride spacer with an
underlying deposited TEOS oxide, that behaves as a convenient etch stop layer, is
a popular choice for sidewall spacer in modern CMOS process flows. In this work
the effect of the silicon nitride spacer process on the B profile in silicon and the
related dose loss of B from the Si into the silicon dioxide has been investigated.
This is reflected as a dramatic decrease in the junction depth. The influence of the
nitride spacer chemistry on B dose loss from the Si has also been investigated.
The different nitride chemistries result in different B dose loss. A new model that
predicts B junction depths and dose loss during fabrication of ultra-shallow
junctions has been developed. A study of the interactions of dopant atoms and
silicon point defects with silicon oxide films during annealing for ultra-shallow
junction formation has been included. A new method for activation of
source/drain junctions by microwave annealing has been proposed.Electrical and Computer Engineerin