Abstract

The main objective of this JESSI project was the development of methods and tools for the analog and mixed analog/digital circuit design. During phase II of the project ('92-'94) major progress was achieved in the area of tools supporting and improving the different steps of the design flow. Based on these results the goals for phase III ('95-'96) were defined, aiming at even more optimized tools to be used in the design flow. TEMIC put the main emphasis on the following topics: In the area of Analog Simulation a design centring tool was evaluated in practical use and substantially enhanced. A prototype tool performing thermal-electrical simulation was developed together with ANACAD. For the development of macro models VHDL-A was tested and the visual programming environment ViCE was created. For the verification of the electrical behaviour of circuits the tool NWB was developed, which is based on netlists. As a requirement for Circuit Synthesis TEMIC performed a systematic analysis and documentation of selected circuit classes. Symbolic analysis techniques were evaluated for the investigation of circuits. For the implementation of knowledge as well as execution of circuit synthesis the tool ACSYN was further enhanced. It is also well suited to explore the property-space of a circuit. The developed Layout Synthesis tool ALSYN was used in production and further enhanced concerning interactivity. Concurrently placement and routing algorithms were improved. A major step in increasing efficiency for analog layout design was done by using these tools. The developed compaction tool CAMBIO-XT was especially applied to layouts being transferred to a new process, showing also big reduction in design time. For the extraction of substrate parasitics improvements were achieved concerning handling of higher frequencies. (orig.)Available from TIB Hannover: F97B906 / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman

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    Last time updated on 14/06/2016