Adaptive PN code synchronisation in DS-CDMA systems

Abstract

Spread Spectrum (SS) communication, initially designed for military applications, is now the basis for many of today's advanced communications systems such as Code Division Multiple Access (CDMA), Global Positioning System (GPS), Wireless Local Loop (WLL) , etc. For effective communication to take place in systems using SS modulation, the Pseudo-random Noise (PN) code used at the receiver to despread the received signal must be identical and be synchronised with the PN code that was used to spread the signal at the transmitter. Synchronisation is done in two steps: coarse synchronisation or acquisition, and fine synchronisation or tracking. Acquisition involves obtaining a coarse estimate of the phase shift between the transmitted PN code and that at the receiver so that the received PN code will be aligned or synchronised with the locally generated PN code. After acquisition, tracldng is now done which involves maintaining the alignment of the two PN codes. This thesis presents results of the research calTied out on a proposed adaptive PN code acquisition circuit designed to improve the synchronisation process in Direct Sequence CDMA (DS-CDMA) systems. The acquisition circuit is implemented using a Matched Filter (MF) for the correlation operation and the threshold setting device is an adaptive processor known as the Cell Averaging Constant False Alarm Rate (CA-CFAR) processor. It is a double dwell acquisition circuit where the second dwell is implemented by Post Detection Integration (PDI). Depending on the application, PDI can be used to mitigate the effect of frequency offset in non-coherent detectors and/or in the implementation of multiple dwell acquisition systems. Equations relating the performance measures - the probability of false alarm (Pra ), the probability of detection (P d) and the mean acquisition time (E {Tacq}) - of the circuit are deri ved. Monte Carlo simulation was used for the independent validation of the theoretical results obtained, and the strong agreement between these results shows the accuracy of the derived equations for the proposed circuit. Due to the combination of PDI and CA-CFAR processor in the implementation of the circuit, results obtained show that it can provide a good measure of robustness to frequency offset and noise power variations in mobile environment, consequently leading to improved acquisition time performance. The complete synchronisation circuit is realised by using this circuit in conjunction with a conventional code tracking circuit. Therefore, a study of a Non-coherent Delay-Locked Loop (NDLL) code tracking circuit is also calTied out.EThOS - Electronic Theses Online ServiceGBUnited Kingdo