The paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three Operational Floating Current Conveyors (OFCCs) and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA) is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematicThe paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three operational floating current conveyors (OFCCs) and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA) is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematic

Ahalawat, Varun Kumar

Kumar, V. Venkatesh

Malhotra, Chetna

Nand, Deva

Pandey, Neeta

Advances in Electrical and Electronic Engineering

Neeta Pandey

Deva Nand

V. Venkatesh Kumar

Varun Kumar Ahalawat

Chetna Malhotra

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Realization of OFCC based Transimpedance Mode Instrumentation Amplifier

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THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 14 | NUMBER: 2 | 2016 | JUNERealization of OFCC based Transimpedance ModeInstrumentation AmplifierNeeta PANDEY, Deva NAND, V. Venkatesh KUMAR, Varun KUMAR AHALAWAT,Chetna MALHOTRADepartment of Electronics and Communication Engineering, Delhi Technological University,Shahbad Daulatpur, Main Bawana Road, Delhi-110042, Indian66pandey@rediffmail.com, devkamboj07@gmail.com, vvenkateshkumar.kumar@gmail.com,varun.ahlawat@gmail.com, chtmalhotra@gmail.comDOI: 10.15598/aeee.v14i2.1551Abstract. The paper presents an instrumentation am-plifier suitable for amplifying the current source trans-ducer signals. It provides a voltage output. It has ahigh gain, common mode rejection ratio and gain in-dependent bandwidth. It uses three Operational Float-ing Current Conveyors (OFCCs) and four resistors.The effect of nonidealities of OFCC on performanceof proposed Transimpedance Instrumentation Amplifier(TIA) is also analyzed. The proposal has been ver-ified through SPICE simulations using CMOS basedschematicThe paper presents an instrumentation am-plifier suitable for amplifying the current source trans-ducer signals. It provides a voltage output. It has ahigh gain, common mode rejection ratio and gain in-dependent bandwidth. It uses three operational float-ing current conveyors (OFCCs) and four resistors.The effect of nonidealities of OFCC on performanceof proposed Transimpedance Instrumentation Amplifier(TIA) is also analyzed. The proposal has been ver-ified through SPICE simulations using CMOS basedschematic.KeywordsDifference amplifier, operational floating cur-rent conveyor, transimpedance instrumentationamplifier.1. IntroductionThe Operational Floating Current Conveyor (OFCC)[1], [2] is a versatile active building block which pro-vides flexibility to the circuit designer. It inherits thefeatures of current conveyor and the current feedbackop-amp with additional current output terminal. Theavailability of both high and low impedance ports at in-put and output provides flexibility to circuit designer.The OFCC has been used for implementing instrumen-tation amplifier [3], read out circuit [4], logarithmicamplifier [5], rectifier [6], filters [7], [8], [9], [10], [11],variable gain amplifier [12], and wheatstone bridge [13].An Instrumentation Amplifier (IA) is invariably usedas an input block in applications such as automotivetransducers [14], industrial process control [15], [16],[17], linear position sensing [18] and bio-potential ac-quisition systems [19], [20], [21], [22], [23], [24] to am-plify differential signals and to suppress unwanted com-mon mode signals. Generally the operational amplifierbased IA are classified as Voltage Mode IA (VMIA)whereas current mode building block based IA are re-ferred as Current Mode IA (CMIA). Another way toclassification is based on the type of input and outputsignal on which IA is working. The TransimpedanceIA (TIA) is one among such classification where thesensed current is amplified and converted into a volt-age. There is limited literature available on TIAs [25],[26], [27], and no OFCC based TIA is available in openliterature to the best of author’s knowledge. The de-tails of available TIAs are comprehended in Tab. 1 ac-cording to the number and type of active and passiveelements used along with the impedance presented atinput and output. The following points are observedfrom Tab. 1:• The opamp based topology [26] uses excessivenumber of resistors.• The input impedance is low for [27] which isideal for current sensing whereas a high inputimpedance is presented for [25], [26].c© 2016 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 162THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 14 | NUMBER: 2 | 2016 | JUNE• The output impedance of [26], [27] is proper i.e.low in contrast to the one provided by [25].• Extra active elements are required for impedancematching at input [25], [26] and output [25].Tab. 1: Characteristics of available instrumentation amplifiers.Ref. Active No. of Input Outputno. elements resistors impedance impedance[25] 2 CCII+ 3 High High[26] 3 opamps 10 High Low[27] 3 OTRA 5 Low LowIt is clear from the above discussion that only topol-ogy [27] provides proper input and output impedancelevels and does not require additional circuitry forimpedance matching. The aim of this paper isto present an OFCC based TIA offering proper in-put/output interface. It uses three active blocks andfour resistors i.e. same number of active blocks as [27]and the lesser passive components than [27]. Both in-put and output impedances of proposed topology arelow.The paper is organized in five sections as follows:Section 2. briefly discusses the basic characteristics ofOFCC and detailed description of proposed TIA struc-ture. Section 3. describes behavior of proposed TIAin presence of nonidealities. The simulation results arepresented in Section 4. followed by conclusions inSection 5.2. Proposed CircuitThe key component of the proposed circuit is theOFCC block as shown in Fig. 1. It has two inputs(X, Y) and three outputs (W, Z+, Z-).XYWZ+OFCC Z-iX IwiYIZ-IZ+VwVZ-VZ+VXVYFig. 1: OFCC block.The port X is a low impedance current input whilethe port labeled Y is a high impedance voltage in-put. The ports Z+ and Z- are high impedance cur-rent outputs, where Z+ has positive polarity and Z-has negative polarity. The terminal marked W is thelow impedance output voltage terminal. The terminalcharacteristics of the OFCC are characterized by thematrix given in Eq. (1):IYVXVWIZ+IZ− =0 0 0 0 01 0 0 0 00 Zt 0 0 00 0 1 0 00 0 −1 0 0VYIXIWVZ+VZ− , (1)where open loop transimpedance gain Zt is impedancebetween the ports X and W and other symbols havetheir usual meanings.XXXYYYWWWZ+Z+Z+OFCC1 Z-Z-Z-iin1iin2iw1iw2v0R1R1R2RGOFCC2OFCC3Fig. 2: Proposed OFCC based TIA.Figure 2 shows the proposed TIA circuit. It con-sists of three OFCCs and four resistances. The thirdOFCC block in Fig. 2 is simply used as a current tovoltage convertor which converts the amplified differ-ence of currents that has been received as an inputto OFCC1 and OFCC2, into voltage. The differentialtransimpedance gain of the instrumentation amplifierfor an ideal case is computed as follows.The currents (iw1, iw2) flowing out of W terminalsof OFCC1 and OFCC2 respectively, are:iw1 = −[iin1 +R1RG(iin1 − iin2)], (2)iw2 = −[iin2 +R1RG(iin2 − iin1)]. (3)The output voltage is computed as:vout = −R2(−iw1 + iw2) = R2(iw1 − iw2) ==[(iin2 − iin1)(1 +2R1RG)].(4)Using Eq. (4), the differential gain (Ad) is obtained as:Ad =voutiin2 − iin1 =(1 +2R1RG)R2. (5)c© 2016 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 163THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 14 | NUMBER: 2 | 2016 | JUNE3. Non Ideal AnalysisPractically, there are two kinds of OFCC non-idealities.The first type of nonidealities comes from tracking er-rors between port voltages and currents and their ef-fect depend strongly on topology. As the Y terminalin proposed topology is grounded the performance isunaffected due to voltage tracking errors. Consideringthe current tracking error, the currents at Z+ and Z-terminals are represented as:iZ+ = αiw2, (6)iZ− = −γiw1, (7)where α and γ are non ideality constants.Therefore, Eq. (4) modifies to:vout =[(αiin2 − γiin1) + . . .. . .+((α+ γ)R1RG(iin2 − iin1))]R2.(8)Assuming α = γ = 1 in Eq. (8) the differential gain(Ad) is written as:Ad =voutiin2 − iin1 =(1 +2R1RG)R2. (9)Considering iin1 = iin2 = icm in Eq. (8) for com-mon mode operation, the common mode gain (Acm) isobtained as:Acm =vouticm= (α− γ)R2. (10)Therefore the CMRR of the final circuit is:CMRR =AdAcm=1α− γ(1 +2R1RG). (11)The second nonideality comes due to finite tran-simpedance gain Zt and its frequency dependencewhich is approximated as Zt = 1/(sCp) at high fre-quencies. The value of Cp is (Zto ωtc), where Zto andωtc represent open loop transimpedance gain and itscut off frequency respectively.Considering finite Zt, Eq. (4) is recalculated asvout = [1(s)iw1 − 2(s)iw2]3(s)R2, (12)vout =[((iin2 − iin1)(2(s)− 1(s)) R1RG)+ . . .. . . (2(s)iin2 − 1(s)iin1)]3(s)R2,(13)where i(s) =11 + sCpiR1for i = 1, 2 and 3(s) =11 + sCp3R2.Assuming 1(s) = 2(s), differential gain is calcu-lated as:Ad =(1 +2R1RG)R2uc, (14)where uc =11 + sCp3R2· 11 + sCp1R1and is uncom-pensated error function.Taking iin1 = iin2 = icm the common mode gain isgiven by:Acm =sR1R2(Cp1 − Cp2)(1 + sCp1R1)(1 + sCp2R1)(1 + sCp3R2). (15)Therefore the CMRR becomes:CMRR =AdAcm==(1 +RG2R1)(2 + sR1(Cp1 + Cp2)s(Cp2 − Cp1)RG).(16)4. Simulation ResultsThe CMOS based OFCC implementation [12] as shownin Fig. 3, is used for verifying functionality of proposedTIA. The transistor aspect ratios are given in Tab. 2.SPICE simulations are carried out using supply volt-ages of ±1.5 V and bias voltages of ±0.8 V. The simu-lated differential gain response of the proposed TIA isdepicted in Fig. 4 for RG = 1 kΩ, R1 = 5 kΩ and R2is varied from 1 kΩ to 3 kΩ in step of 1 kΩ in order toobtain different gains. The CMRR frequency responseis shown in Fig. 5. It may be noted that CMRR isindependent of gain and has a bandwidth of 112 kHz.Figure 6 shows the noise spectral analysis of the pro-posed TIA using the same component values as thosetaken for obtaining differential gain response. It is ob-served that the output noise level has small magnitude.The power consumption of the proposed OFCC basedTIA is found to be 1.5 mW.M5M1M2M3 M4M6 M7M8M9M13M11M12 M14M10 M15VB1VB2Y X W Z+ Z-M16 M18M17M19M21M20Fig. 3: CMOS schematic of OFCC [12].5. ConclusionIn this paper, an OFCC based TIA is presented andsimulated. The circuit requires only three OFCCs,c© 2016 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 164THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 14 | NUMBER: 2 | 2016 | JUNETab. 2: Characteristics of available instrumentation amplifiers.Transistor W (µm)/L (µm)M1, M2 50/1M3, M4, M11, M12, 50/2.5M14, M16, M18, M20M5, M7, M10, M15, 20/2.5M17, M19, M21M6, M8 40/2.5M9, M13 100/2.5Fig. 4: Frequency response of the proposed TIA.Fig. 5: CMRR of the proposed TIA for different gain values.Fig. 6: Noise spectral density for different values of gain.three feedback resistors and one grounded resistor. Itworks with current mode of input in order to pro-duce an amplified output without using complex de-signs. The AC analysis proves the efficiency of thisnew circuit and the huge bandwidth it possesses. Theproposed topology offers advantages over the existingoperational amplifiers based TIAs, in terms of a widerbandwidth that stays independent of the finite openloop gain of the TIA. The proposed circuit also of-fers low component count as compared to the existingOTRA based design.References[1] KHAN, A. A., M. A. AL-TURAIGI and M.A. EL-ELA. Operational floating current con-veyor: Characteristics, Modeling and appli-cations. In: IEEE Instrumentation and Mea-surement Technology Conference. Hamamatsu:IEEE, 1994, pp. 788–790. ISBN 0-7803-1880-3.DOI: 10.1109/IMTC.1994.351887.[2] GHALLAB, Y. H., M. A. EL-ELA and M.ELSAID. Operational floating current con-veyor: Characteristics, Modeling and Exper-imental results. In: Proceedings of Interna-tional Conference on Microelectronics. Kuwait:IEEE, 1999, pp. 59–62. ISBN 0-7803-6643-3.DOI: 10.1109/ICM.2000.884805.[3] GHALLAB, Y. H., W. BADAWY, K. V. I. S.KALER and B. J. MAUNDY. A Novel Current-Mode Instrumentation Amplifier Based on Opera-tional Floating Current Conveyor. IEEE Transac-tions on Instrumentation and Measurement. 2005,vol. 54, no. 5, pp. 1941–1949. ISSN 0018-9456.DOI: 10.1109/TIM.2005.854254.[4] GHALLAB, Y. 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IEEE Transactions on Biomedical Circuitsc© 2016 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 166THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 14 | NUMBER: 2 | 2016 | JUNESystems. 2008, vol. 2, iss. 1, pp. 44–49. ISSN 1932-4545. DOI: 10.1109/TBCAS.2008.921601.[25] WILSON, B. Universal conveyor instrumen-tation amplifier. Electronic Letters. 1989,vol. 25, iss. 7, pp. 470–471. ISSN 0013-5194.DOI: 10.1049/el:19890323.[26] AGOURIDIS, D. C. and R. J. FOX.Transresistance instrumentation amplifier.Proceedings of the IEEE. 1978, vol. 66,iss. 10, pp. 1286–1287. ISSN 0018-9219.DOI: 10.1109/PROC.1978.11125.[27] PANDEY, R., N. PANDEY and S. K. PAUL.Electronically tunable transimpedance instrumen-tation amplifier based on OTRA. Journal of En-gineering. 2013, vol. 2013, iss. ID 648540, pp. 1–5.ISSN 2051-3305. DOI: 10.1155/2013/648540.About AuthorsNeeta PANDEY did M.Tech. (Microelectronics)from Birla Institute of Technology and Sciences, Pilani,Rajasthan, India and Ph.D. from Guru Gobind SinghIndraprastha University, Delhi, India. At present she isAssociate Professor in Department of Electronics andCommunication Engineering, Delhi Technological Uni-versity, Delhi. A life member of ISTE, and a member ofIEEE, USA. She has published papers in International,National Journals of repute and conferences. Her re-search interests are in Analog and Digital VLSI Design.Deva NAND did B.Tech (Electronics and Commu-nication Engineering), M.Tech (Microelectronics andVLSI Design) from Kurukshetra University, Kuruk-shetra, India and he is pursuing Ph.D. from DelhiTechnological University, Delhi, India. At present heis Assistant Professor in Department of Electronicsand Communication Engineering, Delhi TechnologicalUniversity, Delhi, India. His research interests includeAnalog Mixed Signal VLSI Design and Digital VLSIDesign.V. Venkates KUMAR pursuing B.Tech (Elec-tronics and Communication Engineering) from DelhiTechnological University, Delhi, India. His researchinterests include Analog VLSI Design.Varun KUMAR AHALAWAT pursuing B.Tech(Electronics and Communication Engineering) fromDelhi Technological University, Delhi, India. Hisresearch interests include VLSI Design.Chetna MALHOTRA pursuing B.Tech (Elec-tronics and Communication Engineering) from DelhiTechnological University, Delhi, India. Her researchinterests include Analog Electronics and VLSI Design.c© 2016 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 167

Realization of OFCC based transimpedance mode instrumentation amplifier

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Realization of OFCC based transimpedance mode instrumentation amplifier

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