We evaluate an oscillator-amplifier MMIC submitted to high-temperature operating life time tests. To relate adequately these results with individual components’ results, it is important to realise that failure mechanisms in non-linear MMICs are governed by the maximally instantaneous voltages/currents and hence that comparisons should be conducted at equal instantaneous conditions

Beyer, A.

De Raedt, W.

Nauwelaers, B.

Neuhaus, B.

Schreurs, D.

Vandersmissen, R.

English

AMS Acta

CORRELATION BETWEEN THE RELIABILITY OF HEMT DEVICESAND THAT OF A COMBINED OSCILLATOR-AMPLIFIER MMICD. Schreurs, W. De Raedt   , R. Vandersmissen   , B. Neuhaus    , A. Beyer    , and B. NauwelaersK.U.Leuven, Div. ESAT-TELEMIC, Kasteelpark Arenberg 10, B-3001 Leuven, BelgiumE-mail: dominique.schreurs@esat.kuleuven.ac.be, Fax: +32-16-321986, Phone: +32-16-321821 IMEC, Div. MCP, Kapeldreef 75, B-3001 Leuven, Belgium   Gerhard-Mercator University, Dept. of Electr. Eng., Bismarckstr. 81, D-47057 Duisburg, GermanyABSTRACTWe evaluate an oscillator-amplifier MMIC submitted to high-temperature operating life time tests. To relate adequatelythese results with individual components’ results, it is important to realise that failure mechanisms in non-linear MMICsare governed by the maximally instantaneous voltages/currents and hence that comparisons should be conducted at equalinstantaneous conditions.INTRODUCTIONThe microwave and millimetre wave market for circuits and systems based on GaAs pHEMTs is steadily growing. Animportant aspect for MMICs to be inserted in commercial applications is reliability. To evaluate the reliability of the GaAspHEMT MMIC technology, we have designed and fabricated a combined oscillator-amplifier MMIC and submitted thiscircuit to high temperature operating life time tests. These stress test results will be related to the reliability of the circuit’sindividual components.DESIGN AND RELIABILITY OF THE OSCILLATOR-AMPLIFIER MMICCircuit designThe test vehicle used to evaluate the reliability of the GaAs pHEMT MMIC technology is a 5 GHz microstrip combinedoscillator-amplifier. We choose the topology of an oscillator followed by a buffer amplifier, because in this way theamplifier is RF stressed by the oscillator as soon as DC bias is applied. Hence, RF stress test conditions are obtained,whereas only a DC bias has to be applied to the MMIC located in the furnace during the life time tests. The oscillationfrequency (5 GHz) is relatively low considering that GaAs pHEMTs are the active devices. The reason is that we alsowant to study the possible degradation of the typical lumped passive components in an MMIC technology.In general, an oscillator consists of a negative resistance and a resonator. The negative resistance is principally obtained bydestabilising the pHEMT at the desired oscillation frequency. As resonator, we choose an on-chip lumped element basedconfiguration, despite its low Q compared to off-chip resonators, because it is the purpose to evaluate the reliability of thepHEMT MMIC technology and not that of possible external components. The actual oscillation frequency is determinedby the parallel resonant circuit formed by the input capacitance (  + 	 ) of the HEMT in the oscillator subcircuit and aspiral inductor. We added a MIM capacitor in parallel to the transistor’s gate to minimise the sensitivity of the oscillationfrequency to processing variations. The widths of the HEMTs in the oscillator and amplifier subcircuits are 50  m and100  m, respectively. Because a robust design was required for the envisaged reliability tests, parallel feedback is used inthe amplifier topology to ensure broadband stabilisation. The non-linear GaAs pHEMT model used in both the oscillatorand amplifier designs is an in-house developed look-up table model (1). A picture of the oscillator-amplifier MMIC isshown in Figure 1. The design is compact (1.5 mm x 1.2 mm), because the bias networks act simultaneously as matchingcircuits. The output power is 3 dBm, while the higher order harmonics are suppressed with more than 30 dB.Reliability test preparationThe fabricated oscillator-amplifier MMICs have to be properly prepared for the reliability tests. The MMIC needs to bepackaged to prevent any contamination with air. The package has to be put on an MIC carrier to facilitate DC biasingduring the stress test and to enable RF measurements at regular time points. It is also necessary to have a test-fixture thatis compatible with the MIC carrier to perform calibrated RF measurements.After finishing the processing, the wafers are tested for DC and RF functionality. Consequently, the wafers are diced andthe individual chips are mounted into a ceramic Kyocera package by using a conductive glue (preform Au   Sn   ). Toavoid low frequency oscillations, chip capacitors are put in the package as close as possible to the DC bonding pads. Thewire bond connecting the oscillator RF output to the feed-line of the package has to be as short as possible to minimise itsinductive effect on the MMIC performance. The package is mounted on an alumina carrier by conductive glue. Supple-mentary bias networks are added off-chip to enhance the circuit’s stability in the kHz and MHz frequency bands. Afterverifying the DC functionality, the package is hermetically sealed. Figure 2 shows the picture of a package containingtwo oscillator chips and corresponding bias circuitry, that is mounted on the alumina substrate. All the additional SMDand chip components must be well suited to the thermal environment. Therefore, we tested the SMD capacitors separatelyin the furnace at the considered temperatures. No degradation was noticed after 1000 hours. The alumina substrate isrealised in coplanar waveguide technology, which prevents the processing of via holes. Furthermore, a better groundconnection between the package and the MIC carrier is guaranteed due to the absence of the inductive contribution of thevia holes. Finally, in order to perform RF measurements, the MIC carrier can be mounted in a test-fixture, that provides atransition between the coplanar waveguide alumina MIC and a coaxial SMA connector.High temperature operating life time testThe mounted MMICs are submitted to a high temperature operating life time test. The furnace temperature is  = 175  Cand the number of circuits for this test is 9. At regular time points, the DC characteristics of the HEMTs of both sub-circuits are measured. Also the output power and the oscillation frequency are monitored. The most dominant changeduring the test is a decreased threshold voltage ff . The order of the fi decrease, which is about -80 mV, is the samefor both the oscillator HEMT (Figure 3) and the amplifier HEMT. The drain-source current flffi and the transconductance  in the linear region decrease slightly ( ! 7 " ), which can be attributed mainly to the ff decrease. The fi decrease isaccompanied by a decrease in the input capacitance, which results in an increase in the oscillation frequency, as is shownin Figure 4. The variation on this shift, which is between 4 MHz and 70 MHz, is rather large. One can compare thisto the variation of the oscillation frequency when the gate-source voltage $#  of the oscillator HEMT is varied at roomtemperature by the same amount, which corresponds to 10 MHz. The difference between these shifts can be explained bythe fact that during the reliability test also the   and the input capacitance of the amplifier HEMT change and hence theload presented to the output of the oscillator is modified. We will try to explain the physical cause of the   decrease inthe next Section, by correlating these circuit reliability results under high temperature RF operating conditions with thereliability results of the constituting components and especially the GaAs pHEMTs.RELIABILITY OF THE INDIVIDUAL COMPONENTSIn order to clarify the changes of the oscillator performance as function of stress time, it is necessary to examine thereliability of its constituting elements. First, we shortly focus on the passive components, before we examine three testsperformed on the active devices. The first test done on the GaAs pHEMTs is a high temperature operating life time test,where a DC bias has been applied to the devices in the furnace. The second test is a high temperature storage test, whereno DC bias is applied. The third test involves an operating life time test at room temperature.Reliability of passive componentsThe passive components present in the investigated MMIC are microstrip lines, air bridges, spiral inductors, an activelayer resistor, MIM capacitors and via-holes. We did not explicitly perform reliability tests on these passive components,but estimated their possible degradation based on the well covered analyses available in literature (2,3). In this way, it isdetermined that dielectric breakdown in the MIM capacitors is very unlikely to happen, because all voltage levels in theinvestigated MMIC are relatively low. Also, we do not expect that electromigration will happen in the microstrip lines,spiral inductors and airbridges, because the nominal current density is less than 40 % of the critical current density forelectromigration. Electromigration will also not be present in the active layer resistor, because no DC current is flowingthrough the resistor. However, the resistance value may shift due to ohmic contact degradation. A resistance shift in thevia holes may be noticed due to differential thermal expansion. This will result in a reduced DC current.High temperature operating life time test on GaAs pHEMTsThe high temperature operating life time test has been performed on passivated GaAs pHEMTs. After wafer dicing, thesingle devices are packaged and hermetically sealed in TO18 packages. The furnace has a dry nitrogen atmosphere toavoid lead oxidation and/or contamination. Since the long DC wires by which the DC bias is applied can cause low-frequency oscillations, an SMD capacitor is put between the gate and the source leads. The furnace temperature   is175  C and the devices are biased for normal amplifier operation. The DC $#  is kept fixed on 0 V and the DC drain-sourcevoltage  ffi is adjusted to obtain a DC fl ffi equal to 200 mA/mm. During the tests, the gate-source current fl#  and fl ffichanges are monitored in situ and DC measurements at room temperature are performed at intermediate time points.Figure 5 shows the change of fi in the linear region. During the first days, we notice a slight negative ff shift, whichis probably related to thermal enhanced electron trapping (4). After about 100 hours, another failure mechanism be-comes apparent since the   becomes more positive. It is gate sinking, which is related to the Schottky gate contactdegradation (5,6). The gate contact of the studied technology consists of Ti(50 nm)/Pt(50 nm)/Au(350 nm). The gatesinking effect could be minimised by using Mo or WSi as the barrier material (7), but it has to be noted that the showntests were performed on a standard GaAs pHEMT technology where no special technology modifications were yet donewith regard to reliability improvement. At  %'& (*),+  C, the positive shift of   is about 45 mV. This becomes110 mV in case of a similar test performed at  %-& ./.,0  C. The fl ffi decreases by about 2.4 mA/mm, which canbe caused by an increase of the channel resistance and/or the ohmic source and drain resistances. The increase of theopen channel resistance is expected when gate sinking occurs (2). The second possible reason for the 1324 decrease couldbe ohmic contact degradation. However, it has been reported (2) that degradation of the used type of ohmic contacts(AuGe(120 nm)/Ni(15 nm)/Au(60 nm)) only becomes dominant at a temperature higher than 200 5 C.As an intermediate conclusion, we can state that there is no direct correlation between the dominant failure mechanismof the oscillator-amplifier MMIC and the case where single HEMTs are DC stressed at conditions of amplifier operation,because the sign of the 6fi7 shift is opposite.High temperature storage test on GaAs pHEMTsThe high temperature storage test has been performed at a furnace temperature of 8:9;%<=?>@>@A/5 C on 11 packaged GaAspHEMTs. Figure 6 shows the behaviour of 6 7 as function of stress time. The 6 7 decreases about 110 mV. A negativeshift of 6 7 can be explained by positive charge under the gate. This positive charge can be created by the thermal activatedprocess to trap electrons. Similar negative 6 7 shifts in GaAs pHEMTs at high temperature storage test conditions havebeen reported (4). This physical phenomenon is normally accompanied by an increase in 124 , whereas we measured adecrease of 124 as function of time. This decrease of 124 can be explained by a second failure mechanism that is active atthese stress conditions, which is ohmic contact degradation.We notice here a similar behaviour as in the case of the oscillator-amplifier MMIC, namely a negative 6ff7 shift. However,it is our opinion that this thermal activated process is not the dominant failure mechanism in the MMIC case. A reasonis that we estimated from separate tests that the channel temperature of the devices during the oscillator stress tests is notmuch higher than the ambient temperature.Operating life time test at room temperature on GaAs pHEMTsThe previously described reliability tests were all thermal tests. In this paragraph, electrical stress tests at room temper-ature will be discussed. In a previous study (8), the effect of hot electron stress was studied on the same GaAs pHEMTtechnology. The change in device performance was evaluated by DC and RF characterising the samples before and after60 min. stress at 6$B 4 = 0 V and 6 24 = 5.5 V. This test introduced a negative 6 7 shift by about 60 to 70 mV. This decrease iscaused by a build-up of positive charge underneath the gate. The positive charge accumulation is likely due to deep trapscapturing holes generated by impact ionisation and flowing towards the gate.Our opinion is that the physical cause of the 6ff7 decrease during the oscillator stress test is most probably due to impactionisation. The measured output power of the MMIC is about 3 dBm. Since the MMIC output was left open (unloaded)while the circuit was located in the furnace, the maximal AC drain voltage is doubled compared to the 50 C case, andhence impact ionisation conditions are temporarily reached during the RF cycle.CONCLUSIONSWe have investigated the results of a high temperature operating life time test on a non-linear MMIC, being a combinedoscillator-amplifier. To clarify the observations, we examined the reliability of the constituting components and especiallythe GaAs pHEMTs. By conducting and analysing several stress tests on these active elements, we showed that the mostdominant failure mechanism happening in the studied MMIC is impact ionisation.These experiments are a good illustration of the conclusion that the failure mechanisms occuring in a non-linear MMICare governed by the maximally instantaneous voltages/currents and hence that comparisons with other reliability testsshould be conducted at equal instantaneous conditions.ACKNOWLEDGEMENTSR. Vandersmissen acknowledges the IWT for its financial support. D. Schreurs is supported by the Fund for ScientificResearch-Flanders as a post-doctoral fellow.REFERENCES(1) D. Schreurs et al., “Automated generation of intrinsic large-signal HEMT models from S-parameter measurements”, 1995, Mi-crowave and Optronics Conf., pp. 106–110.(2) A. Christou, Reliability of Gallium Arsenide MMICs, 1992, John Wiley & Sons.(3) J. Pasquali, “Failure mechanisms of GaAs MMIC qualification methodology”, 1993, ESREF, pp. 21–23.(4) E. Zanoni et al., “A new degradation mechanism induced by DX-centers in AlGaAs/InGaAs PM-HEMT’s”, 1994, ESSDERC,pp. 539–542.(5) C. Chen et al., “Reliability study on pseudomorphic InGaAs power HEMT devices at 60 GHz”, 1994, IEEE MTT-S, pp. 817–820.(6) K. Christianson et al., “Failure mechanisms in AlGaAs/GaAs HEMTs”, Solid State Electronics, 1995, pp. 1623–1626.(7) P. Conti et al., “Performances and reliability of HEMTs: State of the art and experimental analysis”, 1992, Microelectron. Reliab.,pp. 1577–1583.(8) R. Menozzi et al., “DC and RF instability of GaAs-based PHEMTs due to hot electrons”, 1996, GaAs Reliability Workshop, pp. 18–21.Figure 1: SEM picture of the osc-amp MMIC (1.5 mmx 1.2 mm), taken after c-gate metallisation.Figure 2: Overview picture of the MIC containing 2 pack-aged oscillators and DC bias networks.time [h]DFE10 G10 H10 I101-0.7[V]-0.8-0.9-1-1.1Figure 3: JffK measured at JMLN = 20 mV versus stress timeof the GaAs pHEMT in the osc. subcircuit.time [h]OQPSRUT10 G10 H10 I1015.5[GHz]5.45.35.25.15Figure 4: Oscillation frequency V,WNYX versus stress time ofthe GaAs pHEMT based MMIC oscillator.time [h]DE10 G10 H10 I101-0.6[V]-0.7-0.8-0.9-1Figure 5: J K measured at J LN = 20 mV versus time of100 Z m GaAs pHEMTs ( [:\]%^`_badc@e@f C).time [h]DE10 G10 H10 I101-0.3[V]-0.4-0.5-0.6-0.7-0.8Figure 6: J K measured at J LN = 20 mV versus time of100 Z m GaAs pHEMTs ( [:\]%^_hg@g@i/f C).

Correlation between the reliability of HEMT devices and that of a combined oscillator-amplifier

AMS Acta - Alm@DL - Università di Bologna

CORRELATION BETWEEN THE RELIABILITY OF HEMT DEVICES
AND THAT OF A COMBINED OSCILLATOR-AMPLIFIER MMIC
D. Schreurs, W. De Raedt   , R. Vandersmissen   , B. Neuhaus    , A. Beyer    , and B. Nauwelaers
K.U.Leuven, Div. ESAT-TELEMIC, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
E-mail: dominique.schreurs@esat.kuleuven.ac.be, Fax: +32-16-321986, Phone: +32-16-321821
 
IMEC, Div. MCP, Kapeldreef 75, B-3001 Leuven, Belgium
   Gerhard-Mercator University, Dept. of Electr. Eng., Bismarckstr. 81, D-47057 Duisburg, Germany
ABSTRACT
We evaluate an oscillator-amplifier MMIC submitted to high-temperature operating life time tests. To relate adequately
these results with individual components’ results, it is important to realise that failure mechanisms in non-linear MMICs
are governed by the maximally instantaneous voltages/currents and hence that comparisons should be conducted at equal
instantaneous conditions.
INTRODUCTION
The microwave and millimetre wave market for circuits and systems based on GaAs pHEMTs is steadily growing. An
important aspect for MMICs to be inserted in commercial applications is reliability. To evaluate the reliability of the GaAs
pHEMT MMIC technology, we have designed and fabricated a combined oscillator-amplifier MMIC and submitted this
circuit to high temperature operating life time tests. These stress test results will be related to the reliability of the circuit’s
individual components.
DESIGN AND RELIABILITY OF THE OSCILLATOR-AMPLIFIER MMIC
Circuit design
The test vehicle used to evaluate the reliability of the GaAs pHEMT MMIC technology is a 5 GHz microstrip combined
oscillator-amplifier. We choose the topology of an oscillator followed by a buffer amplifier, because in this way the
amplifier is RF stressed by the oscillator as soon as DC bias is applied. Hence, RF stress test conditions are obtained,
whereas only a DC bias has to be applied to the MMIC located in the furnace during the life time tests. The oscillation
frequency (5 GHz) is relatively low considering that GaAs pHEMTs are the active devices. The reason is that we also
want to study the possible degradation of the typical lumped passive components in an MMIC technology.
In general, an oscillator consists of a negative resistance and a resonator. The negative resistance is principally obtained by
destabilising the pHEMT at the desired oscillation frequency. As resonator, we choose an on-chip lumped element based
configuration, despite its low Q compared to off-chip resonators, because it is the purpose to evaluate the reliability of the
pHEMT MMIC technology and not that of possible external components. The actual oscillation frequency is determined
by the parallel resonant circuit formed by the input capacitance (  + 
	 ) of the HEMT in the oscillator subcircuit and a
spiral inductor. We added a MIM capacitor in parallel to the transistor’s gate to minimise the sensitivity of the oscillation
frequency to processing variations. The widths of the HEMTs in the oscillator and amplifier subcircuits are 50  m and
100  m, respectively. Because a robust design was required for the envisaged reliability tests, parallel feedback is used in
the amplifier topology to ensure broadband stabilisation. The non-linear GaAs pHEMT model used in both the oscillator
and amplifier designs is an in-house developed look-up table model (1). A picture of the oscillator-amplifier MMIC is
shown in Figure 1. The design is compact (1.5 mm x 1.2 mm), because the bias networks act simultaneously as matching
circuits. The output power is 3 dBm, while the higher order harmonics are suppressed with more than 30 dB.
Reliability test preparation
The fabricated oscillator-amplifier MMICs have to be properly prepared for the reliability tests. The MMIC needs to be
packaged to prevent any contamination with air. The package has to be put on an MIC carrier to facilitate DC biasing
during the stress test and to enable RF measurements at regular time points. It is also necessary to have a test-fixture that
is compatible with the MIC carrier to perform calibrated RF measurements.
After finishing the processing, the wafers are tested for DC and RF functionality. Consequently, the wafers are diced and
the individual chips are mounted into a ceramic Kyocera package by using a conductive glue (preform Au   Sn   ). To
avoid low frequency oscillations, chip capacitors are put in the package as close as possible to the DC bonding pads. The
wire bond connecting the oscillator RF output to the feed-line of the package has to be as short as possible to minimise its
inductive effect on the MMIC performance. The package is mounted on an alumina carrier by conductive glue. Supple-
mentary bias networks are added off-chip to enhance the circuit’s stability in the kHz and MHz frequency bands. After
verifying the DC functionality, the package is hermetically sealed. Figure 2 shows the picture of a package containing
two oscillator chips and corresponding bias circuitry, that is mounted on the alumina substrate. All the additional SMD
and chip components must be well suited to the thermal environment. Therefore, we tested the SMD capacitors separately
in the furnace at the considered temperatures. No degradation was noticed after 1000 hours. The alumina substrate is
realised in coplanar waveguide technology, which prevents the processing of via holes. Furthermore, a better ground
connection between the package and the MIC carrier is guaranteed due to the absence of the inductive contribution of the
via holes. Finally, in order to perform RF measurements, the MIC carrier can be mounted in a test-fixture, that provides a
transition between the coplanar waveguide alumina MIC and a coaxial SMA connector.
High temperature operating life time test
The mounted MMICs are submitted to a high temperature operating life time test. The furnace temperature is  = 175  C
and the number of circuits for this test is 9. At regular time points, the DC characteristics of the HEMTs of both sub-
circuits are measured. Also the output power and the oscillation frequency are monitored. The most dominant change
during the test is a decreased threshold voltage ﬀ . The order of the ﬁ decrease, which is about -80 mV, is the same
for both the oscillator HEMT (Figure 3) and the amplifier HEMT. The drain-source current ﬂﬃ
 and the transconductance
 
 in the linear region decrease slightly ( ! 7 " ), which can be attributed mainly to the ﬀ decrease. The ﬁ decrease is
accompanied by a decrease in the input capacitance, which results in an increase in the oscillation frequency, as is shown
in Figure 4. The variation on this shift, which is between 4 MHz and 70 MHz, is rather large. One can compare this
to the variation of the oscillation frequency when the gate-source voltage $#  of the oscillator HEMT is varied at room
temperature by the same amount, which corresponds to 10 MHz. The difference between these shifts can be explained by
the fact that during the reliability test also the   and the input capacitance of the amplifier HEMT change and hence the
load presented to the output of the oscillator is modified. We will try to explain the physical cause of the   decrease in
the next Section, by correlating these circuit reliability results under high temperature RF operating conditions with the
reliability results of the constituting components and especially the GaAs pHEMTs.
RELIABILITY OF THE INDIVIDUAL COMPONENTS
In order to clarify the changes of the oscillator performance as function of stress time, it is necessary to examine the
reliability of its constituting elements. First, we shortly focus on the passive components, before we examine three tests
performed on the active devices. The first test done on the GaAs pHEMTs is a high temperature operating life time test,
where a DC bias has been applied to the devices in the furnace. The second test is a high temperature storage test, where
no DC bias is applied. The third test involves an operating life time test at room temperature.
Reliability of passive components
The passive components present in the investigated MMIC are microstrip lines, air bridges, spiral inductors, an active
layer resistor, MIM capacitors and via-holes. We did not explicitly perform reliability tests on these passive components,
but estimated their possible degradation based on the well covered analyses available in literature (2,3). In this way, it is
determined that dielectric breakdown in the MIM capacitors is very unlikely to happen, because all voltage levels in the
investigated MMIC are relatively low. Also, we do not expect that electromigration will happen in the microstrip lines,
spiral inductors and airbridges, because the nominal current density is less than 40 % of the critical current density for
electromigration. Electromigration will also not be present in the active layer resistor, because no DC current is flowing
through the resistor. However, the resistance value may shift due to ohmic contact degradation. A resistance shift in the
via holes may be noticed due to differential thermal expansion. This will result in a reduced DC current.
High temperature operating life time test on GaAs pHEMTs
The high temperature operating life time test has been performed on passivated GaAs pHEMTs. After wafer dicing, the
single devices are packaged and hermetically sealed in TO18 packages. The furnace has a dry nitrogen atmosphere to
avoid lead oxidation and/or contamination. Since the long DC wires by which the DC bias is applied can cause low-
frequency oscillations, an SMD capacitor is put between the gate and the source leads. The furnace temperature   is
175  C and the devices are biased for normal amplifier operation. The DC $#  is kept fixed on 0 V and the DC drain-source
voltage  ﬃ
 is adjusted to obtain a DC ﬂ ﬃ
 equal to 200 mA/mm. During the tests, the gate-source current ﬂ#  and ﬂ ﬃ

changes are monitored in situ and DC measurements at room temperature are performed at intermediate time points.
Figure 5 shows the change of ﬁ in the linear region. During the first days, we notice a slight negative ﬀ shift, which
is probably related to thermal enhanced electron trapping (4). After about 100 hours, another failure mechanism be-
comes apparent since the   becomes more positive. It is gate sinking, which is related to the Schottky gate contact
degradation (5,6). The gate contact of the studied technology consists of Ti(50 nm)/Pt(50 nm)/Au(350 nm). The gate
sinking effect could be minimised by using Mo or WSi as the barrier material (7), but it has to be noted that the shown
tests were performed on a standard GaAs pHEMT technology where no special technology modifications were yet done
with regard to reliability improvement. At  
%'& (*),+  C, the positive shift of   is about 45 mV. This becomes
110 mV in case of a similar test performed at  
%-& ./.,0  C. The ﬂ ﬃ
 decreases by about 2.4 mA/mm, which can
be caused by an increase of the channel resistance and/or the ohmic source and drain resistances. The increase of the
open channel resistance is expected when gate sinking occurs (2). The second possible reason for the 132
4 decrease could
be ohmic contact degradation. However, it has been reported (2) that degradation of the used type of ohmic contacts
(AuGe(120 nm)/Ni(15 nm)/Au(60 nm)) only becomes dominant at a temperature higher than 200 5 C.
As an intermediate conclusion, we can state that there is no direct correlation between the dominant failure mechanism
of the oscillator-amplifier MMIC and the case where single HEMTs are DC stressed at conditions of amplifier operation,
because the sign of the 6ﬁ7 shift is opposite.
High temperature storage test on GaAs pHEMTs
The high temperature storage test has been performed at a furnace temperature of 8:9
;%<=?>@>@A/5 C on 11 packaged GaAs
pHEMTs. Figure 6 shows the behaviour of 6 7 as function of stress time. The 6 7 decreases about 110 mV. A negative
shift of 6 7 can be explained by positive charge under the gate. This positive charge can be created by the thermal activated
process to trap electrons. Similar negative 6 7 shifts in GaAs pHEMTs at high temperature storage test conditions have
been reported (4). This physical phenomenon is normally accompanied by an increase in 12
4 , whereas we measured a
decrease of 12
4 as function of time. This decrease of 12
4 can be explained by a second failure mechanism that is active at
these stress conditions, which is ohmic contact degradation.
We notice here a similar behaviour as in the case of the oscillator-amplifier MMIC, namely a negative 6ﬀ7 shift. However,
it is our opinion that this thermal activated process is not the dominant failure mechanism in the MMIC case. A reason
is that we estimated from separate tests that the channel temperature of the devices during the oscillator stress tests is not
much higher than the ambient temperature.
Operating life time test at room temperature on GaAs pHEMTs
The previously described reliability tests were all thermal tests. In this paragraph, electrical stress tests at room temper-
ature will be discussed. In a previous study (8), the effect of hot electron stress was studied on the same GaAs pHEMT
technology. The change in device performance was evaluated by DC and RF characterising the samples before and after
60 min. stress at 6$B 4 = 0 V and 6 2
4 = 5.5 V. This test introduced a negative 6 7 shift by about 60 to 70 mV. This decrease is
caused by a build-up of positive charge underneath the gate. The positive charge accumulation is likely due to deep traps
capturing holes generated by impact ionisation and flowing towards the gate.
Our opinion is that the physical cause of the 6ﬀ7 decrease during the oscillator stress test is most probably due to impact
ionisation. The measured output power of the MMIC is about 3 dBm. Since the MMIC output was left open (unloaded)
while the circuit was located in the furnace, the maximal AC drain voltage is doubled compared to the 50 C case, and
hence impact ionisation conditions are temporarily reached during the RF cycle.
CONCLUSIONS
We have investigated the results of a high temperature operating life time test on a non-linear MMIC, being a combined
oscillator-amplifier. To clarify the observations, we examined the reliability of the constituting components and especially
the GaAs pHEMTs. By conducting and analysing several stress tests on these active elements, we showed that the most
dominant failure mechanism happening in the studied MMIC is impact ionisation.
These experiments are a good illustration of the conclusion that the failure mechanisms occuring in a non-linear MMIC
are governed by the maximally instantaneous voltages/currents and hence that comparisons with other reliability tests
should be conducted at equal instantaneous conditions.
ACKNOWLEDGEMENTS
R. Vandersmissen acknowledges the IWT for its financial support. D. Schreurs is supported by the Fund for Scientific
Research-Flanders as a post-doctoral fellow.
REFERENCES
(1) D. Schreurs et al., “Automated generation of intrinsic large-signal HEMT models from S-parameter measurements”, 1995, Mi-
crowave and Optronics Conf., pp. 106–110.
(2) A. Christou, Reliability of Gallium Arsenide MMICs, 1992, John Wiley & Sons.
(3) J. Pasquali, “Failure mechanisms of GaAs MMIC qualification methodology”, 1993, ESREF, pp. 21–23.
(4) E. Zanoni et al., “A new degradation mechanism induced by DX-centers in AlGaAs/InGaAs PM-HEMT’s”, 1994, ESSDERC,
pp. 539–542.
(5) C. Chen et al., “Reliability study on pseudomorphic InGaAs power HEMT devices at 60 GHz”, 1994, IEEE MTT-S, pp. 817–820.
(6) K. Christianson et al., “Failure mechanisms in AlGaAs/GaAs HEMTs”, Solid State Electronics, 1995, pp. 1623–1626.
(7) P. Conti et al., “Performances and reliability of HEMTs: State of the art and experimental analysis”, 1992, Microelectron. Reliab.,
pp. 1577–1583.
(8) R. Menozzi et al., “DC and RF instability of GaAs-based PHEMTs due to hot electrons”, 1996, GaAs Reliability Workshop, pp. 18–
21.
Figure 1: SEM picture of the osc-amp MMIC (1.5 mm
x 1.2 mm), taken after c-gate metallisation.
Figure 2: Overview picture of the MIC containing 2 pack-
aged oscillators and DC bias networks.
time [h]
DFE
10 G10 H10 I101
-0.7
[V]
-0.8
-0.9
-1
-1.1
Figure 3: JﬀK measured at JML
N = 20 mV versus stress time
of the GaAs pHEMT in the osc. subcircuit.
time [h]
OQPSRUT
10 G10 H10 I101
5.5
[GHz]
5.4
5.3
5.2
5.1
5
Figure 4: Oscillation frequency V,WNYX versus stress time of
the GaAs pHEMT based MMIC oscillator.
time [h]
D
E
10 G10 H10 I101
-0.6
[V]
-0.7
-0.8
-0.9
-1
Figure 5: J K measured at J L
N = 20 mV versus time of
100 Z m GaAs pHEMTs ( [:\
]%^`_badc@e@f C).
time [h]
D
E
10 G10 H10 I101
-0.3
[V]
-0.4
-0.5
-0.6
-0.7
-0.8
Figure 6: J K measured at J L
N = 20 mV versus time of
100 Z m GaAs pHEMTs ( [:\
]%^_hg@g@i/f C).


CORRELATION BETWEEN THE RELIABILITY OF HEMT DEVICES
AND THAT OF A COMBINED OSCILLATOR-AMPLIFIER MMIC
D. Schreurs, W. De Raedt
 
, R. Vandersmissen
 
, B. Neuhaus
  
, A. Beyer
  
, and B. Nauwelaers
K.U.Leuven, Div. ESAT-TELEMIC, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
E-mail: dominique.schreurs@esat.kuleuv n.ac.be, Fax: +32-16-321986, Phone: +32-16-321821 
IMEC, Div. MCP, Kapeldreef 75, B-3001 Leuven, Belgium  
Gerhard-Mercator University, Dept. of Electr. Eng., Bismarckstr. 81, D-47057 Duisburg, Germany
ABSTRACT
We evaluate an oscillator-amplifier MMIC submitted to high-temperature operating life time tests. To relate adequately
these results with individual components’ results, it is important to realise that failure mechanisms in non-linear MMICs
are governed by the maximally instantaneous voltages/currents and hence that comparisons should be conducted at equal
instantaneous conditions.
INTRODUCTION
The microwave and millimetre wave market for circuits and systems based on GaAs pHEMTs is steadily growing. An
important aspect for MMICs to be inserted in commercial applications is reliability. To evaluate the reliability of the GaAs
pHEMT MMIC technology, we have designed and fabricated a combined oscillator-amplifier MMIC and submitted this
circuit to high temperature operating life time tests. These stress test results will be related to the reliability of the circuit’s
individual components.
DESIGN AND RELIABILITY OF THE OSCILLATOR-AMPLIFIER MMIC
Circuit design
The test vehicle used to evaluate the reliability of the GaAs pHEMT MMIC technology is a 5 GHz microstrip combined
oscillator-amplifier. We choose the topology of an oscillator followed by a buffer amplifier, because in this way the
amplifier is RF stressed by the oscillator as soon as DC bias is applied. Hence, RF stress test conditions are obtained,
whereas only a DC bias has to be applied to the MMIC located in the furnace during the life time tests. The oscillation
frequency (5 GHz) is relatively low considering that GaAs pHEMTs are the active devices. The reason is that we also
want to study the possible degradation of the typical lumped passive components in an MMIC technology.
In general, an oscillator consists of a negative resistance and a resonator. The negative resistance is principally obtained by
destabilising the pHEMT at the desired oscillation frequency. As resonator, we choose an on-chip lumped element based
configuration, despite its low Q compared to off-chip resonators, because it is the purpose to evaluate the reliability of the
pHEMT MMIC technology and not that of possible external components. The actual oscillation frequency is determined
by the parallel resonant circuit formed by the input capacitance (

+

	
) of the HEMT in the oscillator subcircuit and a
spiral inductor. We added a MIM capacitor in parallel to the transistor’s gate to minimise the sensitivity of the oscillation
frequency to processing variations. The widths of the HEMTs in the oscillator and amplifier subcircuits are 50 m and
100  m, respectively. Because a robust design was required for the envisaged reliability tests, parallel feedback is used in
the amplifier topology to ensure broadband stabilisation. The non-linear GaAs pHEMT model used in both the oscillator
and amplifier designs is an in-house developed look-up table model (1). A picture of the oscillator-amplifier MMIC is
shown in Figure 1. The design is compact (1.5 mm x 1.2 mm), because the bias networks act simultaneously as matching
circuits. The output power is 3 dBm, while the higher order harmonics are suppressed with more than 30 dB.
Reliability test preparation
The fabricated oscillator-amplifier MMICs have to be properly prepared for the reliability tests. The MMIC needs to be
packaged to prevent any contamination with air. The package has to be put on an MIC carrier to facilitate DC biasing
during the stress test and to enable RF measurements at regular time points. It is also necessary to have a test-fixture that
is compatible with the MIC carrier to perform calibrated RF measurements.
After finishing the processing, the wafers are tested for DC and RF functionality. Consequently, the wafers are diced and
the individual chips are mounted into a ceramic Kyocera package by using a conductive glue (preform Au  Sn  ). To
avoid low frequency oscillations, chip capacitors are put in the package as close as possible to the DC bonding pads. The
wire bond connecting the oscillator RF output to the feed-line of the package has to be as short as possible to minimise its
inductive effect on the MMIC performance. The package is mounted on an alumina carrier by conductive glue. Supple-
mentary bias networks are added off-chip to enhance the circuit’s stability in the kHz and MHz frequency bands. After
verifying the DC functionality, the package is hermetically sealed. Figure 2 shows the picture of a package containing
two oscillatorchipsandcorrespondingbiascircuitry, that is mountedon thealuminasubstrate.All theadditionalSMD
andchipcomponentsmustbewell suitedto thethermalenvironment.Therefore,wetestedtheSMD capacitorsseparately
in the furnaceat the consideredtemperatures.No degradationwasnoticedafter 1000hours. The aluminasubstrateis
realisedin coplanarwaveguide technology, which preventsthe processingof via holes. Furthermore,a betterground
connectionbetweenthepackageandtheMIC carrieris guaranteedueto theabsenceof theinductivecontributionof the
via holes.Finally, in orderto performRFmeasurements,theMIC carriercanbemountedin a test-fixture,thatprovidesa
transitionbetweenthecoplanarwaveguidealuminaMIC anda coaxialSMA connector.
High temperature operating life time test
ThemountedMMICs aresubmittedto ahightemperatureoperatinglife timetest.Thefurnacetemperatureis  = 175 C
andthe numberof circuits for this test is 9. At regular time points,the DC characteristicsof the HEMTs of both sub-
circuits aremeasured.Also the outputpower andthe oscillationfrequency aremonitored. The mostdominantchange
during the test is a decreasedthresholdvoltage  . The orderof the  decrease,which is about-80 mV, is the same
for boththeoscillatorHEMT (Figure3) andtheamplifierHEMT. Thedrain-sourcecurrent 
 andthetransconductance  in thelinearregiondecreaseslightly ( ! 7 " ), which canbeattributedmainly to the  decrease.The  decreaseis
accompaniedby adecreasein theinput capacitance,which resultsin anincreasein theoscillationfrequency, asis shown
in Figure4. The variationon this shift, which is between4 MHz and70 MHz, is ratherlarge. Onecancomparethis
to the variationof theoscillationfrequency whenthegate-sourcevoltage $#  of the oscillatorHEMT is variedat room
temperatureby thesameamount,whichcorrespondsto 10MHz. Thedifferencebetweentheseshiftscanbeexplainedby
thefactthatduringthereliability testalsothe   andtheinputcapacitanceof theamplifierHEMT changeandhencethe
loadpresentedto theoutputof theoscillatoris modified.We will try to explain thephysicalcauseof the   decreasein
thenext Section,by correlatingthesecircuit reliability resultsunderhigh temperatureRF operatingconditionswith the
reliability resultsof theconstitutingcomponentsandespeciallytheGaAspHEMTs.
RELIABILITY OF THE INDIVIDUAL COMPONENTS
In order to clarify the changesof the oscillatorperformanceas function of stresstime, it is necessaryto examinethe
reliability of its constitutingelements.First, we shortly focuson thepassive components,beforewe examinethreetests
performedon theactive devices.Thefirst testdoneon theGaAspHEMTsis a high temperatureoperatinglife time test,
wherea DC biashasbeenappliedto thedevicesin thefurnace.Thesecondtestis a high temperaturestoragetest,where
no DC biasis applied.Thethird testinvolvesanoperatinglife time testat roomtemperature.
Reliability of passive components
The passive componentspresentin the investigatedMMIC aremicrostrip lines, air bridges,spiral inductors,an active
layerresistor, MIM capacitorsandvia-holes.We did not explicitly performreliability testson thesepassive components,
but estimatedtheir possibledegradationbasedon thewell coveredanalysesavailablein literature(2,3). In this way, it is
determinedthatdielectricbreakdown in theMIM capacitorsis very unlikely to happen,becauseall voltagelevelsin the
investigatedMMIC arerelatively low. Also, we do not expectthatelectromigrationwill happenin themicrostriplines,
spiral inductorsandairbridges,becausethe nominalcurrentdensityis lessthan40 % of the critical currentdensityfor
electromigration.Electromigrationwill alsonot bepresentin theactive layerresistor, becauseno DC currentis flowing
throughtheresistor. However, theresistancevaluemayshift dueto ohmiccontactdegradation.A resistanceshift in the
via holesmaybenoticeddueto differentialthermalexpansion.Thiswill resultin a reducedDC current.
High temperature operating life time test on GaAs pHEMTs
Thehigh temperatureoperatinglife time testhasbeenperformedon passivatedGaAspHEMTs. After waferdicing, the
singledevicesarepackagedandhermeticallysealedin TO18 packages.The furnacehasa dry nitrogenatmosphereto
avoid leadoxidationand/orcontamination.Sincethe long DC wires by which the DC bias is appliedcancauselow-
frequency oscillations,anSMD capacitoris put betweenthegateandthesourceleads.Thefurnacetemperature  is
175 C andthedevicesarebiasedfor normalamplifieroperation.TheDC $#  is keptfixedon0 V andtheDC drain-source
voltage  
 is adjustedto obtaina DC  
 equalto 200 mA/mm. During the tests,the gate-sourcecurrent #  and  

changesaremonitoredin situandDC measurementsat roomtemperatureareperformedat intermediatetimepoints.
Figure5 shows thechangeof  in the linear region. During thefirst days,we noticea slight negative  shift, which
is probablyrelatedto thermalenhancedelectrontrapping(4). After about100 hours,anotherfailure mechanismbe-
comesapparentsincethe   becomesmorepositive. It is gatesinking, which is relatedto the Schottky gatecontact
degradation(5,6). The gatecontactof the studiedtechnologyconsistsof Ti(50 nm)/Pt(50nm)/Au(350nm). The gate
sinkingeffect couldbeminimisedby usingMo or WSi asthebarriermaterial(7), but it hasto benotedthat theshown
testswereperformedon a standardGaAspHEMT technologywhereno specialtechnologymodificationswereyet done
with regard to reliability improvement. At  
%'& (*),+  C, the positive shift of   is about45 mV. This becomes
110 mV in caseof a similar test performedat  
%-& ./.,0  C. The  
 decreasesby about2.4 mA/mm, which can
be causedby an increaseof the channelresistanceand/orthe ohmic sourceanddrain resistances.The increaseof the
openchannelresistanceis expectedwhengatesinkingoccurs(2). Thesecondpossiblereasonfor the 132
4 decreasecould
be ohmic contactdegradation. However, it hasbeenreported(2) that degradationof the usedtype of ohmic contacts
(AuGe(120nm)/Ni(15nm)/Au(60nm))only becomesdominantat a temperaturehigherthan2005 C.
As an intermediateconclusion,we canstatethat thereis no directcorrelationbetweenthedominantfailuremechanism
of theoscillator-amplifierMMIC andthecasewheresingleHEMTsareDC stressedat conditionsof amplifieroperation,
becausethesignof the 67 shift is opposite.
High temperature storage test on GaAs pHEMTs
Thehigh temperaturestoragetesthasbeenperformedat a furnacetemperatureof 8:9
;%<=?>@>@A/5 C on 11 packagedGaAs
pHEMTs. Figure6 shows the behaviour of 6 7 asfunctionof stresstime. The 6 7 decreasesabout110mV. A negative
shift of 6 7 canbeexplainedby positivechargeunderthegate.Thispositivechargecanbecreatedby thethermalactivated
processto trapelectrons.Similar negative 6 7 shifts in GaAspHEMTsat high temperaturestoragetestconditionshave
beenreported(4). This physicalphenomenonis normally accompaniedby an increasein 12
4 , whereaswe measureda
decreaseof 12
4 asfunctionof time. This decreaseof 12
4 canbeexplainedby a secondfailuremechanismthatis activeat
thesestressconditions,which is ohmiccontactdegradation.
Wenoticehereasimilarbehaviour asin thecaseof theoscillator-amplifierMMIC, namelyanegative 67 shift. However,
it is our opinion that this thermalactivatedprocessis not thedominantfailuremechanismin theMMIC case.A reason
is thatwe estimatedfrom separateteststhatthechanneltemperatureof thedevicesduringtheoscillatorstresstestsis not
muchhigherthantheambienttemperature.
Operating life time test at room temperature on GaAs pHEMTs
Thepreviously describedreliability testswereall thermaltests.In this paragraph,electricalstresstestsat roomtemper-
aturewill bediscussed.In a previousstudy(8), theeffect of hot electronstresswasstudiedon thesameGaAspHEMT
technology. Thechangein deviceperformancewasevaluatedby DC andRF characterisingthesamplesbeforeandafter
60min. stressat 6$B 4 = 0 V and 6 2
4 = 5.5V. This testintroducedanegative 6 7 shift by about60to 70mV. Thisdecreaseis
causedby a build-up of positivechargeunderneaththegate.Thepositivechargeaccumulationis likely dueto deeptraps
capturingholesgeneratedby impactionisationandflowing towardsthegate.
Our opinion is that thephysicalcauseof the 67 decreaseduringtheoscillatorstresstestis mostprobablydueto impact
ionisation.Themeasuredoutputpower of theMMIC is about3 dBm. SincetheMMIC outputwasleft open(unloaded)
while the circuit waslocatedin the furnace,the maximalAC drain voltageis doubledcomparedto the 50 C case,and
henceimpactionisationconditionsaretemporarilyreachedduringtheRFcycle.
CONCLUSIONS
We have investigatedtheresultsof a high temperatureoperatinglife time teston a non-linearMMIC, beinga combined
oscillator-amplifier. To clarify theobservations,weexaminedthereliability of theconstitutingcomponentsandespecially
theGaAspHEMTs. By conductingandanalysingseveralstresstestson theseactive elements,we showedthat themost
dominantfailuremechanismhappeningin thestudiedMMIC is impactionisation.
Theseexperimentsarea goodillustrationof theconclusionthat the failuremechanismsoccuringin a non-linearMMIC
aregovernedby the maximally instantaneousvoltages/currentsandhencethat comparisonswith other reliability tests
shouldbeconductedat equalinstantaneousconditions.
ACKNOWLEDGEMENTS
R. Vandersmissenacknowledgesthe IWT for its financialsupport. D. Schreursis supportedby the Fundfor Scientific
Research-Flandersasa post-doctoralfellow.
REFERENCES
(1) D. Schreurset al., “Automatedgenerationof intrinsic large-signalHEMT modelsfrom S-parametermeasurements”,1995,Mi-
crowaveandOptronicsConf., pp.106–110.
(2) A. Christou,Reliabilityof GalliumArsenideMMICs, 1992,JohnWiley & Sons.
(3) J.Pasquali,“Failuremechanismsof GaAsMMIC qualificationmethodology”,1993,ESREF, pp.21–23.
(4) E. Zanoni et al., “A new degradationmechanisminducedby DX-centersin AlGaAs/InGaAsPM-HEMT’s”, 1994,ESSDERC,
pp.539–542.
(5) C. Chenet al., “Reliability studyonpseudomorphicInGaAspower HEMT devicesat60 GHz”, 1994,IEEE MTT-S, pp.817–820.
(6) K. Christiansonet al., “Failuremechanismsin AlGaAs/GaAsHEMTs”, SolidStateElectronics, 1995,pp.1623–1626.
(7) P. Conti et al., “Performancesandreliability of HEMTs: Stateof theart andexperimentalanalysis”,1992,Microelectron. Reliab.,
pp.1577–1583.
(8) R.Menozzietal., “DC andRFinstabilityof GaAs-basedPHEMTsdueto hotelectrons”,1996,GaAsReliabilityWorkshop, pp.18–
21.
Figure1: SEMpictureof theosc-ampMMIC (1.5mm
x 1.2mm),takenafterc-gatemetallisation.
Figure2: Overview picture of the MIC containing2 pack-
agedoscillatorsandDC biasnetworks.
time [h]
DFE
10G10H10I101
-0.7
[V]
-0.8
-0.9
-1
-1.1
Figure3: JK measuredat JML
N = 20mVversusstresstime
of theGaAspHEMTin theosc.subcircuit.
time [h]
OQPSRUT
10G10H10I101
5.5
[GHz]
5.4
5.3
5.2
5.1
5
Figure4: OscillationfrequencyV,WNYX versusstresstimeof
theGaAspHEMTbasedMMIC oscillator.
time [h]
D E
10G10H10I101
-0.6
[V]
-0.7
-0.8
-0.9
-1
Figure5: J K measured at J L
N = 20 mV versus time of
100 Z m GaAspHEMTs( [:\
]%^`_badc@e@f C).
time [h]
D E
10G10H10I101
-0.3
[V]
-0.4
-0.5
-0.6
-0.7
-0.8
Figure6: J K measured at J L
N = 20 mV versus time of
100 Z m GaAspHEMTs( [:\
]%^_hg@g@i/f C).


Correlation between the reliability of HEMT devices and that of a combined oscillator-amplifier

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