The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits
in the presence of faults. We show how this technique can be applied to metal-oxide-semiconductor
(MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by
bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide
variety of MOS circuit failures, such as stuck-at-zero or stuck-at-one nodes, stuck-open or stuck-closed
transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on
this algorithm. The capabilities and the peformance of this program demonstrate the advantages of
combining switch-level and concurrent simulation techniques
