This paper presents an analytical approach to the design of CMOS cross-coupled inverter sense amplifiers. The effects of the equilibrating transistors and the tail current source on the speed of the sense amplifier are analyzed. An analysis of the offset due to mismatch in various parameters is performed, showing that a complete offset analysis has to account for the cell and bitline structure. A new figure of merit for the offset in the sense amplifier and several new design insights are introduced

Hajimiri, Ali

Heald, Raymond

English

Caltech Authors - Main

DESIGN ISSUES IN CROSS-COUPLED INVERTER SErNSE AMPLIFIER 
A li Hajim iri ', Raymond Hea ld2 
'CIS-023, Stanford University, Stanford, CA 94305-4070, USA 
2SUN Microelectronics, Palo Alto, CA 94303, USA 
ABSTRACT 
This paper presents an analytical approach to the design of CMOS 
cross-coupled inverter sense amplifiers. The effects of the equili- 
brating transistors and the tail current source on the speed of the 
sense amplifier are analyzed. An analysis of the offset due to mis- 
match in various parameters is performed, showing that a complete 
offset analysis has to account for the cell and bitline structure. A 
new figure of merit for the offset in the sense amplifier and several 
new design insights are introduced. 
1. INTRODUCTION 
The CMOS cross-coupled inverter pair is frequently used as a fast 
and reliable sense amplifier. The positive feedback is exploited to 
achieve a fast sensing operation. Several analyses have been done 
on the offset of the cross-coupled pair being used as a sense ampli- 
fier [1],[2],[3]. The approach taken in [1],[2] is based on an empiri- 
cal analysis while [3] presents an analysis of the system which 
results in series of involved analytical formulas for the mismatch. 
While cross-coupled pairs have been studied extensively, the addi- 
tional devices used in practice can alter the basic analysis signifi- 
cantly. In particular, the equilibrating device connected between the 
two differential nodes and the tail current source can significantly 
degrade the performance of the cross-coupled inverters as a sense 
amplifier. Several design insights on how to mitigate their effects on 
the sense amplifier performance can be achieved by performing an 
analysis which takes these devices into account. 
Section 2 reviews the basic analysis of the CMOS cross-coupled 
regenerative response. Section 3 discusses the effect of the gradual 
turning off of the equilibrating device. In section 4 the gradual tum- 
ing on of the tail current source at sensing time is discussed. The 
mismatch effect from various sources is considered in section 5. 
2. BASIC CROSS-COUPLED PAIR ANALYSIS 
We start with the classic analysis of the cross-coupled inverter pair. 
The operation of the cross-coupled pair sense amplifier shown in 
Fig. l a  is based on regeneration in the circuit due to positive feed- 
back. It'can be modeled by its small signal equivalent circuit shown 
in Fig. lb. The equivalent model is based on two simplifying 
assumptions: 1) the current has been flowing in the transistors for a 
long enough time. 2) the equilibrating device can be modeled as an 
ideal switch. Both of these assumptions will be challenged in the 
subsequent sections. The simplified analysis of the Fig. 1 results in 
the following differential equation pair, for the V I  and v2 
dv1 GO G m  -+ - - . v 1 + - . v 2  = 0 
dt C C 
dv2 GO G m  - + - - v 2 + - - v 1  = 0 dt  C C 
where C represents the total parasitic capacitance on regenerative 
nodes and 
Gm = g m n  + gmp 
G ,  = go, + go, 
vl@: MI 
(b) 
Figure 1. The simplified model for the sense amplifier. 
where g,, = g,, = g,, and g, = gm3 =. gm4 represent 
the transconductance of the NMOS and PMOS devices at the begin- 
ning of the operation, respectively; g,, and gOp are the output con- 
ductances of the NMOS and PMOS devices. This pair of equations 
can be decoupled, defining the following variables: 
V d y j  = V I  - v2 
v1+ v2 v,, = -
2 
During the sensing period, our major interest is toward the differen- 
tial voltage which is governed by 
This equation has the following solution 
where 
V d i f f ( t )  = V(0) * 
c -  C 
71 = --- G, Go- G, 
The time required for the output to reach a minimum acceptable 
voltage difference, Vmin  is given by 
t = z l . l n  - G::) 
Note that this sensing time decreases linearly with 7 while it 
changes only logarithmically with Vini t .  Therefore once a large 
enough differential voltage 'to override the offset is established on 
regenerative nodes it is more effective to design for the minimum 
time constant instead of maximizing the initial voltage difference. 
3. GRADUAL TURNING OFF OF THE 
EQUILIBRATING DEVICE 
In this section we will take into account the effect of the finite 
switching time of the equililbrating device. The gradual turning off 
of this device affects the dynamics of the sense amplifier output 
voltage. Fig. 2 represents a more realistic model for the sense 
amplifier in the presence o f  a equilibrating device. The voltage at 
the gate of the M5 can be approximately obtained from the simpli- 
11- 149 
0-7803-4455-3/98/$10.00  1998 IEEE 
++* NMOS without Ci, * " 
V V V 
(b) 
Figure 2. Equivalent circuit for the equilibrating device. 
fied model shown in Fig. 2b. Note that the total gate capacitance of 
the M5 is shown as ci, . In Fig. 2 terms C,  and I,,, represent the 
parasitic capacitances on the control line and equivalent average 
output current of the driver, respectively. Using the approximate 
model shown in Fig. 2b the following expression for the gate volt- 
age of M5 is obtained 
V ,  = V,,-r. t  
where r = Io,,/( Ci, + C p )  is the slope of the voltage transition. 
The above expression can be used to find the conductance of the 
equilibrating device as a function of time. Since this expression is 
going to be used during the firing period of the sense amplifier (i.e. 
M5 tuming off) the common mode voltage of the nodes can be 
approximated as being V d d / 2 .  Note that the following analysis is 
valid irrespective of this particular choice of the initial common- 
mode voltage. Using these approximations Go, can be written as 
This results in the following differential equation for the output dif- 
ferential voltage of the sense amplifier 
The above equation can be solved to give the following solution - 
where 
and 
C 
Zj = - 
Gm 
in which G,,, represents the on conductance of M5, i.e. 
and t f f f f  is the time M5 tums off, i.e. V ,  = V,,/2 - V ,  . 
As can be seen from the above equation for the V(t), making the 
W / L  ratio of the equilibrating device smaller makes the retention 
operation faster. This can be seen intuitively too. Since a large 
device shows a large positive conductance at the regenerative 
nodes, which makers the term Go larger and as a result makes 7 
larger. So every effort should be made to minimize the size of the 
equilibrating device as long as it can equalize the residual voltage 
from last sensing cycle. 
4. GRADUAL CURRENT SOURCE TURNING ON 
The cross-coupled pair sense amplifier usually incorporates a tail 
MOS current source which operates to limit the power dissipation 
and facilitates the equilibrating device operation as shown in Fig. 3. 
The exact time at which this device is turned on is arbitrary to some 
extent. It can be turned on at the same time as the equilibrating 
device is turned off, or it can be tumed on earlier or later. The ear- 
lier this device is tumed on the larger the power dissipation and the 
faster the sensing time. It also affects the offset mismatch in device 
parameters and the charge injection. 
To gain more intuition into the circuit, an analytical approximation 
for this circuit is attempted on the circuit model of Fig. 3. The same 
analysis as the simple cross-coupled pair can be applied assuming a 
time dependent transconductance, g,( t )  , for the MOS devices. 
The transconductance depends on the tail current in the following 
form 
While M6 is in the pinch-off region, the following expression for 
the total G, = gm, + g, can be obtained 
where 
Gm(t) = a ' (Vd,j - V c ,  - V,) 
11- 150 
W,/L,, W,/L,, W,/L, stand for the W / L  ratio of the tail 
current source device, NMOS, and PMOS, respectively, and V,, is 
the voltage on the gate of M6. 
The differential equation governing the differential voltage across 
the sensing nodes is 
Assuming a slope of r for the gate voltage of M6 the following 
solution for the differential equation is obtained I %If t2  
- Vdd 
Figure 3. Current source model 
where v is  the fall time of Vc,y.From the above equation for t = t ,  (2, $) 
V , i f f ( t f >  = V i n i t  e 
The argument of the exponential function is half the value it would 
have if the devices were turned on early. This shows that further 
speed improvements are possible by tuming on these devices ear- 
lier, or faster. The maximum delay penalty is t f / 2 .  
It can be seen that there is a trade-off between the speed advantage 
obtained by turning M6 on earlier and the corresponding increase in 
the power dissipation. It should also be noted that the early tuming 
on of the current source device will eliminate the charge injection 
mismatch due to the switching of the current source device. 
5. MISMATCH EFFECTS 
In this section the effect of mismatch on the sensing operation in an 
SRAM, such as the mismatch in the threshold voltages, WIL ratios, 
mobilities and oxide capacitances for a pair of equal size transistors 
is considered. A complete static analysis of the mismatch should 
take into account the bitline architecture and cell, as well as the 
sense amplifier structure. The structure shown in the Fig. 4a, is the 
model used for this analysis. It includes the pull-up devices, the 
cell, the switching circuitry (which is simply modeled as a lossy 
wire) and the sense amplifier itself. The efficiency of the lossy wire 
is quantified by a. The information about the value of the bit of 
data stored in the cell is embedded in the current difference seen on 
the bitlines, which is the differential current of the cell 
Ice11 = I n  + I p  
This model can be further simplified to the model shown in Fig. 4b. 
The VoSn and Vosp  represent the threshold mismatch of the 
NMOS and PMOS devices, respectively. 
5.1 Threshold Mismatch 
In this subsection we only consider the effect of threshold mismatch 
and in the next subsection we extend the results to other forms of 
static mismatches. 
Assuming small values of the offset in the model of Fig. 4b, an off- 
set voltage in threshold voltage can be translated into a current mis- 
match in the drain with a gain of g m  . Assuming the worst polarity 
for the offset voltages, the maximum effective offset voltage at the 
regenerative nodes is 
Voff.yet 1 ( g m n v o s n  + gmpvo ,vp )Re , , ( t )  II- 
Where g m  and voS are the transconductance and threshold mis- 
match of the corresponding devices, respectively, and Ref-( t )  rep- 
resents the effective resistance seen between the two regenerative 
nodes. This impedance varies drastically as the equilibrating device 
is tumed off. The effective resistance seen between the two termi- 
nals changes from a positive value to a negative value due to posi- 
tive feedback. The behavior of the Reff ( t )  with time can be quite 
complex, but as will be seen shortly, the detail of this behavior with 
time will not affect the final result. From Fig. 4c, it can be seen that 
Ice l l  results in a useful voltage which is a representative of the data 
in the cell being read. This voltage is 
It is the relative size of the useful voltage to the effective offset volt- 
age across the differential nodes that determines the safety margin 
for sensing rather than the absolute value of the offset voltage. We 
define the ratio of the useful voltage across the differential nodes to 
the effective offset voltage as the safety margin. The ratio has the 
advantage of not changing with scaling to lower voltages, so it can 
be chosen as a figure of merit: indicating safety margin of a given 
design 
A v u s e f u l ( t )  = I c e l l .  R , f f ( t )  
AVu.vefu1 - a l c e l l  
A v o  f f re t  g m n v o s n  + g m p v o s p  
Margin = -- - 
As can be seen the Margin does not depend on the variations of the 
RejT( t )  with time to the first order. Therefore this ratio can be used 
as a time-independent figure of merit to indicate the robustness of 
the sense amplifier. This ratio can be interpreted as the ratio of the 
cell current to the equivalent offset current mismatch. So the effec- 
tive offset current is: 
Note that Z,,,,~yet unlike Vo,f .ret ,  does not strongly depend on the 
size of the equilibrating device. 
5.2 Transconductance Mismatch 
The transconductance mismatch can be translated to an equivalent 
threshold mismatch. This mistmatch is mainly due to lithographic 
error in Ws and Ls of the MOS devices, the mismatch in channel 
mobilities and the gate Capacitances. We assume the following 
behavior in the saturation region for the MOS devices: 
Where y is a function of (effective channel length and varies 
between 2 and 1. Applying the differential sensitivity method to the 
above equation we obtain the following for small variations in the 
variables 
Ak AVT AI -+y- = - 
k V T  I 
So the effect of the variations in the transconductance factor, K on 
the output current can be transformed to an equivalent mismatch in 
threshold voltage, as follows 
'offset  = g m n v o s n  + g m p v o s p  
I ,  = ,k( v,, - VT)'  
The AVfT term is the amount of threshold voltage offset that 
would have resulted in the same amount of offset caused by 
transconductance offset. So the worst case offset can be obtained 
,151 
- .  
I 
WordLine  v 
v 
6 (4 
Figure 4. The bitline structure and the offset definitions. 
based on the assumption that all different offset effects are added in 
the worst possible way, i.e. 
Akn ‘ T n  
kn Y 
V*osn = AVTn + - . - 
V*,),sl, = AVTp+- A % .  - VTP 
Ak kP y 
Note that the r- term can be expanded as: 
nAk  - A W  AL A p  AC,, +-+ -+ -  
k w L CL c o x  
For small values of L and/or W the dominant term is the transcon- 
ductance mismatch term; there are two sources for this dominance. 
The term Ak/k  is proportional to 1/L + 1 / W ,  so decreasing L 
and/or W will result in a larger transconductance mismatch term. 
Also due to short channel effects, for shorter Ls the exponent Y will 
decrease. The most important conclusion from the above develop- 
ment is that it is the relative values of the cell current to the effec- 
tive offset current of the sense amplifier that determines the safety 
margin of the sensing. So any measurement, simulation or calcula- 
tion of the sense amplifier offset without considering the effect of 
the cell and bitline structure can result in misleading predictions. 
- 
-I- 
) [clump 
M1 
6. CONCLUSION AND ACKNOWLEDGEMENT 
The detailed analysis of the cross-coupled pair sense amplifier 
shows that the speed of this sense amplifier can deviate from what 
is predicted by the basic theory due to several practical limitations 
on the design. Through an analytical approach these deviations are 
considered, and the trade-offs involved are discussed. Also, a prac- 
tical method to quantify and compare the effect of offset in such a 
sense amplifier is developed. 
The authors would like to acknowledge SUN Microelectronics and 
the global SRAM group where this work was done. 
7. REFERENCES 
[ 13 N. Ieda, Y. Ohmori, K. Takeya, and T. Yano, “Single Transis- 
tor MOS RAM Using a Short-Channel MOS Transistor,” IEEE 
Journul of Solid-State Circuits, Ed. SC-13, No. 2, April 1978. 
[2]  H. Geib, W. Weber, E. Wohlrab, and L. Risch, “Experimental 
Investigation of the Minimum Signal for Reliable Operation of 
DRAM Sense Amplifiers.” IEEE Journal of Solid-State Circuits, 
Vol.25, N0.3, July 1992. 
[3] R. Sarpeshkar, J.L. Wyatt, N.C. Lu, and P.D. Gerber, “Analysis 
of Mismatch Sensitivity in a Simultaneously Latched CMOS 
Sense Amplifier,” IEEE Trans. on Circuits and Systems-II, Vol. 39, 
No.5, Muy 1992. 
11- 152 


Design issues in cross-coupled inverter sense amplifier

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