A flip-chip waveguide coupler with an order of magnitude greater alignment tolerance than competing approaches is presented for the first time. Experimental data for an "optical jumper" agree with simple design considerations. Application to a planar lightwave circuit-based surface mount photonics platform is outlined

Blauvelt, Henry A.

Lee, Robert B.

Paslaski, Joel S.

Vahala, Kerry J.

Vernooy, David W.

English

Caltech Authors - Main

IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 1, JANUARY 2004 269
Alignment-Insensitive Coupling for PLC-Based
Surface Mount Photonics
David W. Vernooy, Member, IEEE, Joel S. Paslaski, Associate Member, IEEE, Henry A. Blauvelt, Member, IEEE,
Robert B. Lee, Member, IEEE, and Kerry J. Vahala, Member, IEEE
Abstract—A flip-chip waveguide coupler with an order of mag-
nitude greater alignment tolerance than competing approaches
is presented for the first time. Experimental data for an “optical
jumper” agree with simple design considerations. Application to a
planar lightwave circuit-based surface mount photonics platform
is outlined.
Index Terms—Integrated optics, integrated optoelectronics, op-
tical planar waveguide components, optical planar waveguide cou-
plers.
I. INTRODUCTION
ONE OF THE most challenging aspects of optoelectronicpackaging is efficient and robust power transfer from ac-
tive devices to single-mode fibers. Motivated by the success of
hybrid microelectronic packaging, including flip-chip surface
mounting and printed wiring board (PWB) techniques, we em-
brace a similar vision for optoelectronics in which planar light-
wave circuits (PLCs) function as PWBs [1]–[3]. In contrast to
the active alignments commonly required in high-end devices
today, the viability of this approach hinges upon its potential for
low-cost passively aligned power transfer to the PLC platform,
while maintaining high single-mode coupling efficiency [4]. To
address this need, a new scheme for optical coupling between
initially separate waveguides is introduced in this letter that is
capable of lossless power transfer. Its most remarkable charac-
teristic is a “flat-top” alignment insensitivity that is expected
to be a key enabler of the surface mount photonics (SMP) para-
digm. A program for the utilization of this technique with active
device structures for SMP-enabled optoelectronics packaging is
included.
II. END-FIRE COUPLING (EFC), MODE INTERFERENCE
COUPLING (MIC), AND ADIABATIC COUPLING (ADC)
It is instructive to compare the offset sensitivity of three tech-
niques for optical power transfer between symmetric waveg-
uides in a medium of index at a wavelength . A Gaussian
approximation to the waveguide modes (waist and Rayleigh
range ) is used where applicable for simplicity. In
Manuscript received May 9, 2003. revised August 27, 2003.
D. W. Vernooy, J. S. Paslaski, H. A. Blauvelt, and R. B. Lee are with
Xponent Photonics, Inc., Monrovia, CA 91016 USA (e-mail: dvernooy@
xponentinc.com).
K. J. Vahala is with the Department of Applied Physics, California Institute
of Technology, Pasadena, CA 91125 USA.
Digital Object Identifier 10.1109/LPT.2003.819392
EFC, the coupling sensitivity to an offset error
is given by the well-known expression
(1)
with . EFC becomes extremely sensitive to
for the small values of typical of semiconductor-based
devices that have been optimized for performance. MIC occurs
between parallel uniform guides close enough together to be
coupled via their modal exponential tails, which are assumed
to have a decay length in the vertical direction. This
evanescent coupling rate takes the form
(2)
Complete power transfer requires a specific “flopping length”
of along the optical axis, and obeys [5]
(3)
rendering MIC also very sensitive to positioning errors in all
three directions. To transfer power, ADC utilizes variation of
some waveguide property along the optical axis, such as core
index, thickness, or width. Under the unrestrictive assumptions
that retains the form of (2) and the propagation constants of
the individual modes vary linearly at a rate along the coupler,
it is found that
(4)
for long enough coupler lengths [6]. In the limit of
sufficiently strong coupling and slow -variations, ADC
thus, displays the following remarkable properties: 1)
permits 100% power transfer between guides with no critical
dimensions in the design; and 2) is independent of place-
ment errors , demonstrating characteristic “flat-top” offset
tolerances laterally and complete longitudinal independence
for . Adiabaticity also implies fault tolerance to
most operational and fabrication errors, making ADC a robust
high-performance broad-band solution to the coupling problem
and ideally suited to PLC implementation.
III. DESIGN AND EXPERIMENT
To validate these predictions, we designed and fabricated [7]
the “optical jumper” depicted in Fig. 1(a). The layer structure
and refractive indexes of Fig. 1(b) were chosen
1041-1135/04$20.00 © 2004 IEEE
270 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 1, JANUARY 2004
Fig. 1. Flip-chip ADC “jumper” experimental configuration. (a) A
three-dimensional view showing guide widths tapering from 2.5 to 0.5 m
along the jumper, input, and output PLC guides. The guides were overlapped
to have the same width at approximately the taper mid-points. A uniform,
1-mm-long guide in the jumper, and corresponding gap in the PLC guides,
separated input and output. (b) A cross section mid-taper after flip-chipping
illustrating offsets (x ; y ) as well as layer thicknesses and refractive indexes.
to give modes representative of modern active devices. The
flip-chip configuration leverages the tightly controlled vertical
tolerances maintained by deposition and etching processes
common in the semiconductor industry. For experimental ease,
the jumper was designed for transverse-electric polarization
at 1300 nm. An ADC length of m
[Fig. 1(a)] is safely within the adiabatic regime. Simple linear
tapering of the waveguide core width was used for maximal
tolerance to lithographic errors. The wafers were processed
using standard silica-on-silicon PLC fabrication techniques
[1]. After dicing, the jumper die was held with constant force
straddling the input and output PLC guides, which were on a
separate substrate, by a flip-chip bonder with a repeatability
of 0.25 m. The substrate was mounted on a stage which
had a resolution of 0.1 m in order to measure transmission
through the structure of Fig. 1(a) as a function of relative
jumper-substrate position.
IV. RESULTS AND DISCUSSION
Fig. 2 demonstrates the lateral placement tolerance of
along with calculations using (4) and the beam
propagation method (BPM). With defined as the offset for
which remains within 0.1 dB of its peak, the measured
lateral flat-top of m closely matches predictions.
In contrast, EFC and MIC tolerances are 5 to 10 times
tighter and do not display this flat-top feature. The excess
insertion loss of two ADC interfaces was 0.15 dB relative to
cofabricated calibration structures over a measurement-limited
bandwidth of 100 nm. The origin of this loss was traced to
the blunt lithographic points of the tapers 0.5 m through
rigorous BPM studies. The calculated sensitivity for vertical
errors is shown in Fig. 3, assuming the gap is filled with
material of index . Again, the jumper displays an
offset insensitivity to the transmission with a vertical flat-top
of nm. The extent to which errors along
Fig. 2. Jumper “flat-top” measurements demonstrating x  1:5 m,
along with calculations for the ADC device of Fig. 1. Predictions for EFC and
MIC in an appropriately comparable configuration are also shown.
Fig. 3. Calculated curves for the vertical placement errors assuming the gap is
filled with an index n = n . In our case, the flip-chip configuration along
with standard semiconductor processing tolerances ensures negligible error in
this dimension.
Fig. 4. Expected vertical sensitivity of the 0.1-dB fat-top width x to a
vertical gap of index n . Unwanted coupling between axes of this form is
extremely limited in our design.
the two transverse axes are coupled depends upon the gap
refractive index. Fig. 4 illustrates that the sensitivity of to
vertical errors is reduced for increasing gap index . In
the worst case, for example, an air gap of at least 125 nm is
required to reduce by a factor of two. Scanning electron
VERNOOY et al.: ALIGNMENT-INSENSITIVE COUPLING FOR PLC-BASED SMP 271
Fig. 5. Measured ADC z tolerance is 50 times greater than either EFC or
MIC predictions. The device only fails when z reaches the adiabatic length
L  250 m. Note the scale change along the horizontal axis for the EFC
and MIC curves.
microscopy studies, on the other hand, verified our jumper
design achieved intimate contact extremely reproducibly. In
fact, a single jumper piece was used to produce all of the data
in Fig. 1 without noticeable degradation in performance. Fur-
thermore, overcladding thickness tolerances were 40 nm,
negligibly impacting according to the curve.
The measurements in Fig. 5 confirm the jumper is completely
tolerant to errors of order , whereas, EFC and MIC are
50 times more sensitive along the optical axis.
V. APPLICATION TO A PLC-BASED SMP PLATFORM
The application of ADC to optoelectronics packaging in-
volves five key steps: 1) monolithic integration of glass-based
waveguides with etched-facet semiconductor devices [8];
2) passively aligned surface mount ADC of these devices to
the silica-based PLC; 3) mode-expansion of the PLC guide to
a fiber mode size [9]; 4) monolithic self-aligned V-grooves for
passive fiber placement [10]; and 5) glob-top encapsulation
of the complete packaged device to eliminate the need for
hermetic packaging. Wafer-scale processing of steps 1, 3, and 4
leverages any necessary precision alignments over many parts
at once. Of particular importance, step 1 can be accomplished
using standard low-temperature dielectric deposition tech-
niques consistent with III–V device processing. In fact, modern
process flows already abundantly make use of these materials
for alignment, masking, and passivation. Hence, the ADC
coupler in SMP-enabled active devices can closely resemble
the passive jumper reported here.
Exploration of the design and process window for the appli-
cation of ADC to an SMP platform based on this prescription
has been extremely encouraging and will be reported elsewhere.
There is tremendous design flexibility for the ADC interface due
to the forgiving nature of the adiabatic limit.
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Alignment-insensitive coupling for PLC-based surface mount photonics

A novel method for fabrication of a PLC platform for hybrid integration of an optical module by passive alignment,”

Analytic solutions for linearly tapered directional couplers,”

Diode Lasers and Photonic Integrated Circuits.

Efficient coupling of a semiconductor laser to an optical fiber by means of a tapered waveguide on silicon,”

Glass waveguides on silicon for hybrid optical packaging,”

Hybrid integration of semiconductor lasers with Si-based single-mode ridge waveguides,”

Hybrid integration of spot-size converted laser diode on planar lightwave circuit platform by passive alignment technique,”

Integrated optic adiabatic devices on silicon,”

Integration of a laser diode with a polymer-based waveguide for photonic integrated circuits,”

PLC hybrid integration technology and its application to photonic components,”

https://authors.library.caltech.edu/7179/1/VERieeeptl04.pdf

Alignment-insensitive coupling for PLC-based surface mount photonics

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