This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2nd order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices

Acharyya, Amit

Dutta, Asudeb

Jha, P

Naik, J

P, Rajalakshmi

Patra, P

Singh, Shiv Govind

Acharyya, A

Singh, S G

Dutta, A

Name not available

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS

Research Archive of Indian Institute of Technology Hyderabad

A Reconfigurable Medically Cohesive BiomedicalFront-End with Σ∆ ADC in 0.18µm CMOSPankaj Jha, Pravanjan Patra, Jairaj Naik, Amit Acharya, P. Rajalakshmi, Shiv Govind Singh, Ashudeb DuttaDepartment of Electrical Engineering, Indian Institute of Technology Hyderabad, India-502205Email: jovialjha@gmail.com; pravanjanpatra80@gmail.com; kr.jairaj.naik@gmail.com; asudeb dutta@iith.ac.inAbstract—This paper presents a generic programmableanalog front-end (AFE) for acquisition and digitization ofvarious biopotential signals. This includes a lead-off detec-tion circuit, an ultra-low current capacitively coupled signalconditioning stage with programmable gain and bandwidth, anew mixed signal automatic gain control (AGC) mechanismand a medically cohesive reconfigurable Σ∆ ADC. The fullsystem is designed in UMC 0.18µm CMOS. The AFE achievesan overall linearity of more 10 bits with 0.47µW powerconsumption. The ADC provides 2nd order noise-shapingwhile using single integrator and an ENOB of ∼11 bits with5µW power consumption. The system was successfully verifiedfor various ECG signals from PTB database. This system isintended for portable batteryless u-Healthcare devices.I. INTRODUCTIONCardiovascular diseases (CVDs) have been reported tocause most number of deaths globally [1]. This calls fora system which focuses not only on curing the illness(hospital-centric approach), but also on prevention and earlydetection of symptoms (patient-centric approach). Contin-uous electrocardiogram (ECG) monitoring of biosignalsbecome mandatory for such systems. All this, augmentedwith the radical advancement in CMOS and wireless com-munication technologies, has given impetus to concept ofu-Health (ubiquitous healthcare) and use of wireless bodyarea network (WBAN) based applications [2]-[4].Lately there has been a spur in the number of researchand publications related to self-powered acquisition systemsfor body sensor nodes (BSN). Incorporating energy har-vesting mechanism can endow BSNs an indefinite lifetime.An ultra-low power system rendering the functionality ofacquiring, processing and transmitting is presented in [5].The BSN chip is powered by the energy harvested fromhuman body heat through a thermoelectric generator (TEG).Another batteryless acquisition system powered by an adap-tive RF scheme is reported in [6]. Reference [7] presents anexcellent review on self-sustainable systems. Some relatedworks make their system reconfigurable also. Such a systemwith different types of monitoring is described in [8].The block diagram of the proposed ultra-low powersystem for acquisition and digitization is shown in Fig. 1.The prime features of the system are:1) Leadoff detection circuit. The subsequent blocksare powered on only if the signal Lead − off islow [9].2) An ultra-low power two stage capacitive-coupledsignal conditioning circuit (AFE). Apart from pro-viding programmable amplification, it also includestunable 2nd order highpass and lowpass character-istics. Hence it is useful as a generic scheme foracquisition of various biopotential signals (ExG)with different bandwidth and dynamic ranges orgain requirements.3) An efficient gain control (AGC) mechanism tomaintain the input of the ADC to an optimum levelfor which the ADC provides maximum SNR. Inall of the acquisition schemes (even those wheregain is controlled via DSP) reported till date, theADC is kept continuously on. Hence, the presentscheme is envisaged to consume lesser power thanthe conventional ones becausea) ADC is turned on only after AGC hasfinished its job, andb) it avoids gain control through a DSP whichis very power hungry [10].4) A low power high resolution discrete-time (DT)Σ∆ ADC that achieves 2nd order noise shapingwhile using a single integrator. The high resolutionis justified as followsa) Accuracy of the classification and featureextraction algorithms processing the outputof the ADC are proportional to the resolu-tion of the ADCs. Hence the high ENOBachieved here is more medically cohesiveto diagnosis, similar to the data availableat [11].b) It extends the utility of the scheme for thedigitization of a wide range of ExG signals[12].5) Seamless Σ∆ ADC resolution reconfigurabilitywith minimal hardware and almost zero poweroverhead.a) This facilitates the digital circuit, follow-ing the Σ∆ ADC, to reduce its powerconsumption by opting to process lowresolution data. The proposed Σ∆ ADCimplementation aids area and power cost-efficient switching between the two modesvis-a-vis other ADC architectures e.g. SARADC, pipeline ADC, etc.b) Facilitates reconfigurability between lowand high resolution for preliminary andfinal diagnostics, respectively.978-1-4244-9270-1/15/$31.00 ©2015 IEEE 833Fig. 1. Block diagram of the proposed acquisition system.Fig. 2. Analog front-end providing both amplification and LPF and HPFcharacteristics. (M=10, N=8, CU=1.03pF , Cg=103fF , and CL=2-12pF ).An input signal strength from 0.1mV to 1mV is considered here.c) Since the noise power at ADCs input isinversely proportional to AFE′s gain, thisscheme provides a choice between lowand high resolution for high and low gain,respectively.II. MOS TRANSISTOR LEVELIMPLEMENTATION OF INDIVIDUAL BLOCKSA. Signal Conditioning Stage with Programmable Gain andTunable BandwidthIn this work, the signal conditioning stage is imple-mented as a two stage amplifier with capacitive feedback(see Fig. 2). The pair of nodes connected are (2,1), (4,1),(6,1) and (8,1). The connection between the pairs (2,3), (4,5),(6,7) and (8,9) is avoided due to the problem related to gateleakage current of the OTA input transistors [13]. Also it isimportant to keep the HPF cut-off frequency below 50mHz,else the output waveform exhibits a slight ramp for each T-Psegment. The heart of each of the stages is a fully differentialrecyclic folded cascode (RFC) OTA adopted from [14]-[16].All the transistors are operated in weak inversion to obtainsuch low drain currents.The voltage gain of the closed loop amplifier is varied bychanging the feedback factor. Coincidentally, this feedbackresistor also determines the HPF cutoff frequency of theAFE, which is supposed to remove the low frequency noiseand dc offset [17]. Realizing a pole ∼ 0.25Hz-1Hz, wouldrequire a very high resistance. The high resistance valueis obtained using a tunable pseudo-resistor [19] .While theFig. 3. Block diagram of the peak detector and voltage level detector.The digital output and the control signals generated are also shown. HereC=30pF and Idc=92pA.Fig. 4. Plots showing automatic gain control using the peak detector. Thefigure shows the input (top and bottom left) and output (top and bottomright) wavefroms of the AFE for an input signal strength of 0.1mV to 1mV,respectively. The output of the peak detector is shown in brown color.high pass cutoff frequency is varied by changing the gatevoltage of the pseudo-resistor, the lowpass cut-off frequencyis varied changing the load capacitance CL. Further, a T-feedback network is used to reduce the effective feedbackcapacitance so that the same gain can be achieved with muchsmaller capacitance [20].B. Automatic Gain ControlGain of the system is controlled using a peak detector,digital control logic and a logic isolation block whichdecouples the gain control mechanism from the analog frontend once the input falls in the desired amplitude range [21]-[22]. Fig. 3 shows the scheme for peak and voltage leveldetection. The peak detector is adopted from [23]. The OTAof the peak detector is a low power folded cascode amplifierwith all its transistors operating in weak inversion.Also, the peak detector is designed such that it’s totaldischarge time is higher than the time duration between twoR peaks. Hence, here the discharge time is kept greater than1s to prevent the digital control logic from varying the gainduring low amplitude peaks (P,Q,T) of the ECG signal [24].Fig. 4 shows that the voltage level detector is able to generatethe required digital output for proper selection of capacitorsfrom the capacitor bank (see Fig. 2) such that output V0satisfies 0.93V ≤ V0 ≤ 1.05V , as expected.C. Opamp-shared Σ∆ ADCA conventional DT cascaded integrator feedback (CIFB)Σ∆ modulator with 2nd order noise shaping is chosen forthis work. Owing to the fact that the integrator is the mostpower hungry block of the Σ∆ ADC, twofold strategy wasemployed to minimize the ADCs power consumption. First,the whole ADC was designed for as minimum current as834Fig. 5. Single ended representation of the fully differential opamp sharedDT Σ∆ ADC . The circuit renders 1st order noise shaping when onlycomponents in black color are activated, and 2nd order noise shapingwhen the components in dark red are also activated. Here CS1=1.3428pF ,CS2=2.136pF , CS fb=0.79pF , Ci1=8.132pF , Ci2=4.066pF and Vcm=0.9V . Here φ1 and φ2 are the two non-overlapping clock phases, Vrefpand Vrefn are positive and negative reference voltages , and, Q and Q arethe ADC’s output and it’s compliment respectively.Fig. 6. Variation of SFDR with input amplitude for the Σ∆ ADC in Fig.6.possible keeping the target SNR intact. Second, the 2nd ordernoise shaping was achieved using only a single integrator,which reduces the power consumption to nearly half that ofthe ADC employing two integrators. The plot of variationof the spurious free dynamic range (SFDR) with inputamplitude ( see Fig. 6 ) is used to determine the optimuminput level of the ADC, and hence the gain ratios requiredfrom the AFE. The integrator is implemented using theenhanced recyclic folded cascode (ERFC) [14]-[16]. TheERFC OTA has twice the bandwidth of a conventional foldedcascode OTA for the same power and area.D. Seamless ADC Resolution ReconfigurabilityThe output of the Σ∆ ADC is taken up by the subsequentdigital circuit for relevant signal processing like classifi-cation and feature extraction. Since the power consumedby this digital circuit is proportional to the resolution ofthe data it is processing, the digital circuit may opt toreduce its power consumption by reducing the resolutionof the data it is processing. A control signal from thedigital subsequent digital classification and feature extractioncircuit selects the output resolution of the Σ∆ ADC. Theproposed Σ∆ ADC is designed to work in two modescontrolled by the digital block (1) the low resolution (6-8bits), and (2) high resolution (10-12 bits) mode. In the firstmode the Σ∆ modulator provides 1st order noise shapingusing one integrator. In the second mode the Σ∆ ADCmodulator provides 2nd order noise shaping, while usingonly a single integrator. Since integrators are the most powerhungry circuit in the Σ∆ ADCs, here, a higher resolution isextracted keeping the power consumption nearly the same.III. RESULTSThe performance of the AFE and the ADC are tabulatedin Table I and Table II, respectively. The figure of merit forthe ADC are defined as in (1).FOM1 =Power(W ) ∗ 10122SNR(dB)−1.766.02 ∗ 2 ∗BW (Hz)pJ/Conv. (1)TABLE I. AFE PERFORMANCEParameter ValueThis work [25] [19] [26]Technology (µm) 0.18 0.35 0.35 0.18Voltage Supply (V) 1.8 2.5 1 1Power Consumption (µW ) 0.47 0.62 0.9 0.8CMRR (dB) 110 70 71.2 60DC Gain (dB) 40-60 40.7 45.6-60 34Bandwidth (Hz) 0.25-250 5m-200 4.5m-290 0.2-5.8kNEF 6.4 1.96 3.26 2.79TABLE II. OPAMP SHARED Σ∆ ADC PERFORMANCEParameter ValueThis work [27] [28]Technology (µm) 0.18 0.18 0.18Voltage Supply (V) 1.8 0.9 0.7Order 2nd 2nd 2ndBandwidth (Hz) 500 10k 8kFs (kHz) 64 5 1024Power Consumption (µW ) 5.0652 200 80Dynamic Range (dB) 70 83 75FOM1 (pJ/Conv.) 1.96 0.866 1.087TABLE III. QUALITY ASSESSMENT OF THE RECONSTRUCTEDSIGNALParameter ValuePercent Root Mean Square Difference (PRD) 86.11Root Mean Square Error 2.03e-6Signal to Noise Ratio (dB) 41.29Maximum Amplitude Error (MAE) 9.05e-6R-squared Score 0.99Frequency response of the AFE is shown in Fig. 7.The tunability of the AFE (in terms of gain, HPF andLPF cut-off frequency) to match different bandwidth andamplification requirements, evinces the utility of this systemfor the acquisition of various ExG signals. The plot forspectral density of the ADC’s output is shown in Fig. 8.The figure clearly shows that the ADC renders 2nd ordernoise shaping and SNR of 70dB. The complete systemwas validated for a scaled ECG signal taken from the PTBdatabase [11]. The digital output of the Σ∆ ADC ( streamof 1s and 0s ) generated by the Spectre simulator is exportedto Matlab Simulink, where it is passed through a CIC filterto reconstruct the ECG signal. The quality assessment of thereconstructed signal wrt. the input ECG signal is tabulated inTable III [30], [29]. As is shown in Fig. 9 (bottom most) thereconstructed waveform captures all the essential features ofthe ECG signal.IV. CONCLUSIONAn ultra-low power acquisition and digitization systemis presented. While the AFE does the job of filtering andamplification, the Σ∆ modulator ADC digitizes the output.All the blocks are implemented in UMC 0.18µm CMOStechnology. Each block is designed with minimum currentconsumption. Power dissipation is further saved by hard-ware sharing and keeping the ADC turned off during the835Fig. 7. Frequency response of the AFE. The high pass cut-off frequencyis tuned by the gate potential Vctrl of the pseudo-resistor. Different highpass cut-off frequency for different values of Vctrl is shown.Fig. 8. PSD of the opamp shared Σ∆ ADC for an input of -5.2dB.Fig. 9. The topmost waveform is the input ECG signal. The centerwaveform is obtained with connection between the pairs (2,3), (4,5), (6,7)and (8,9) as shown in Fig. 2 . The waveform exhibits slight ramp for eachT-P segment. The bottom most waveform is the correct output signal, withthe connection pairs (2,1), (4,1), (6,1) and (8,1).initial phase of operation. All the blocks meet the desiredexpectations. The scheme is tested with scaled version ofvarious ECG signals taken from PTB database. The qualityassessment of the reconstructed signal wrt. the input ECGsignal reveals it’s fidelity. The overall system consumes ∼6µW power. This system is useful for u-Healthcare.REFERENCES[1] Global status report on noncommunicable diseases 2010. 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A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS

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