Speech recognition applications challenge traditional out-of-order processors because of low cache locality and poor branch behavior. We observe that these symptoms may be mitigated my exploiting the existing parallelism in these algorithms. In this project, we exploit many levels of parallelism in Sphinx, a leading speech recognition system, to improve architectural utilization by decreasing cache miss rates and improving branch prediction. The resulting parallel implementation will be evaluated in several single and multiprocessor systems. Additionally, we plan to evaluate Sphinx in the novel M3T architecture.
The contribution of this project can be classified as threefold: parallelizing Sphinx, evaluating it in several single processor and multiprocessor systems, and analyzing M3T's effectiveness in executing Sphinx. All the evaluations are performed with a new simulation environment developed especially for chip-multiprocessor environments
