Reference-free detection of semiconductor assembly defect

Abstract

This paper aims at developing a novel defect detection algorithm for the semiconductor assembly process by image analysis of a single captured image, without reference to another image during inspection. The integrated circuit (IC) pattern is usually periodic and regular. Therefore, we can implement a classification scheme whereby the regular pattern in the die image is classified as the acceptable circuit pattern and the die defect can be modeled as irregularity on the image. The detection of irregularity in image is thus equivalent to the detection of die defect. We propose a method where the defect detection algorithm first segments the die image into different regions according to the circuit pattern by a set of morphological segmentations with different structuring element sizes. Then, a feature vector, which consists of many image attributes, is calculated for each segmented region. Lastly, the defective region is extracted by the feature vector classification. © 2005 SPIE and IS&T.published_or_final_versio