DSD 2007, 10th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, Aug. 27 - 31, 2007, Lubeck, Germany, pp. 280-287.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper focuses on numerical function generators
(NFGs) based on k-th order polynomial approximations.
We show that increasing the polynomial order k reduces
signicantly the NFG's memory size. However, larger k
requires more logic elements and multipliers.numerical function generators
(NFGs) based on k-th order polynomial approximations.
We show that increasing the polynomial order k reduces
signicantly the NFG's memory size. However, larger k
requires more logic elements and multipliers. To quantify this tradeoff, we introduce the FPGA utilization measure, and then determine the optimum polynomial order k. Experimental results show that: 1) for low accuracies (up to 17 bits), 1st order polynomial approximations produce the most efficient implementations; and 2) for higher accuracies (18 to 24 bits), 2nd-order polynomial approximations produce the most efficient implementations
