Several different hardware structures for Fast Fourier Transform (FFT) are discussed in this thesis. VHDL was used in providing a simulation. Various costs and performance comparisons of different FFT structures are revealed. The FFT system leads to a design of Discrete Cosine Transform (DCT). VHDL allows the hierarchical description of a system in structural and behavioral description. In the structural description, a component is described in terms of an interconnection of more primitive components. However, in the behavioral domain, a component is described by defining its inputoutput response in terms of a procedure. In this thesis, the lowest hierarchy level is chip-level. In modeling of the floating point unit AMD29325 behavior, several basic functions or procedures are involved. A number of AMD29325 chips were used in the different structures of the FFT butterfly. The full pipeline structure of the FFT butterfly, controller, and address sequence generator are simulated in VHDL. Finally, two methods of implementation of the DCT system are discussed.http://archive.org/details/discretecosinetr1094527602Captain, Republic of China (Taiwan) ArmyApproved for public release; distribution is unlimited
