Contains an introduction, reports on two research projects and a list of publications.Joint Services Electronics Program Contract DAAL03-92-C-0001Joint Services Electronics Program Grant DAAH04-95-1-0038Raytheon Corporation Contract 90-58203Texas Instruments Agreement dated 08/14/9

Adams, Tracy E.

del Alamo, Jesús A.

Reiner, James W.

Somerville, Mark H.

Weinberg, Michael J.

DSpace@MIT

Chapter 2. Heterostructure Field-Effect TransistorsChapter 2. Physics of InAIAs/InGaAs HeterostructureField-Effect TransistorsAcademic and Research StaffProfessor Jesis A. del AlamoGraduate StudentsMark H. SomervilleUndergraduate StudentsTracy E. Adams, James W. ReinerTechnical and Support StaffMichael J. Weinberg2.1 IntroductionSponsorsJoint Services Electronics ProgramContract DAAL03-92-C-0001Grant DAAH04-95-1-0038Raytheon CorporationContract 90-58203Texas InstrumentsAgreement dated 08/14/91The goal of this project is to develop InAIAs/InGaAsheterostructure field-effect transistors suitable formillimeter-wave high-power applications. The suit-ability of this material system for low-noise amplifi-cation is now unquestionable. Obtaining a highbreakdown voltage is, however, still rather difficult,and it usually comes with severe trade offs. Thisfact seriously limits the suitability of this materialsystem for high-power millimeter-wave applications.Over the last few years, we have been engaged inresearch on how to improve the breakdown voltageof InAIAs/InGaAs HFETs, that is, the maximumvoltage that the device can handle. Our work hasprovided technological design criteria that are now1 S.R. Bahl, W.J. Azzam, and J.A. del Alamo, "Strained-InsulatorIEEE Trans. Electron Dev. 38(9): 1986-1992 (1991).widely used in industry, such as employingAlAs-rich InAIAs pseudoinsulators' and carrying outselective recessed-mesa sidewall isolation.2 Wealso recently identified the detailed physical mech-anisms responsible for breakdown inInAIAs/n+-InGaAs HFETs fabricated at MIT. 3 Wefound that the breakdown path involves two dif-ferent processes in series. First, electronthermionic field emission takes place from the gateover the InAIAs barrier into the InGaAs channel.This is followed by hot electron relaxation in thechannel with impact ionization of electron-holepairs. More recently, in collaboration with Daimler-Benz in Ulm, Germany, we identified the samemechanisms in action in state-of-the-artInAIAs/InGaAs Modulation-Doped Field-Effect Tran-sistors (MODFETs). 4 Finally, last year we identifiedthe existence of substantial impact ionization in thechannel of our own InAIAs/InGaAs HFETs underregular operating conditions. This is important forunderstanding noise in these devices.In the last period of performance, we have devel-oped S-passivation technology for InAIAs/InGaAsMODFETs, and we have integrated it into a com-plete 0.8 pm gate length device process. Spassivation is claimed to reduce Fermi level pinningInAl,_As/n-Ino53Gao 7,As Heterostructure Field-Effect Transistors,"2 S.R. Bahl and J.A. del Alamo, "Elimination of Mesa-Sidewall Gate-Leakage in InAIAs/InGaAs Heterostructures by Selective SidewallRecessing," IEEE Electron Dev. Lett. 13(4): 195-197 (1992).3 S.R. Bahl and J.A. del Alamo, "Physics of Breakdown in InAIAs/n -InGaAs Heterostructure Field-Effect Transistors," IEEE Trans.Electron Dev. 41(12): 2268-2275 (1994).4 S.R. Bahl, J.A. del Alamo, J. Dickmann, and S. Schildberg, "Off-State Breakdown in InAIAs/InGaAs MODFETs," IEEE Trans. Elec-tron Dev. 42(1): 15-22 (1995).Chapter 2. Heterostructure Field-Effect Transistorsat the surface of Ill-V compound semiconductors.There are two ways in which this could be exploitedto improve the power handling capability ofInAIAs/InGaAs MODFETs. First, if the Fermi levelcan be unpinned, S passivation at the exposed gapbetween the gate and the drain should smooth theelectric field at the drain end of the channel. Thisought to result in an improvement of the breakdownvoltage. Furthermore, if S passivation is applied tothe interface between an appropriate gate metaland the semiconductor, the Schottky barrier heightof the gate could be improved. This should result ina reduction of gate leakage and an improvement ofthe breakdown voltage. Our first experimentalresults indicate modest improvements in theexpected direction but it is yet unclear the physicsthat are at play. The following sections describe inmore detail our technical findings and our key con-clusions.2.2 An Integratable S-passivationProcess for the InAIAs/InGaAs SystemFor several years, the use of sulfur-containing com-pounds for the passivation of the surfaces of bothGaAs and InP has received considerable attention.It has been demonstrated that treatment with sulfur-containing compounds prior to evaporation canyield substantial shifts in Schottky barrier heighttowards the ideal value dictated by the metal workfunction.5 Recently, similar results were reported forAu Schottky barriers on InAIAs. 6 While these resultsoffer great promise, it is unclear whether theimprovement in Schottky barrier height on InAlAs isdue to reduction in pinning, or to a shift in the posi-tion of the pinned Fermi level. Furthermore, thework reported previously has utilized aggressivesurface cleans prior to sulfur treatment. An effectiveS passivation process that is suitable to integrationwith a complete HFET fabrication process has yetto be developed.Based on a literature search, we selected (NH4)2Sxas the most likely candidate for an integratable Streatment of the InAIAs surface. We first carried outtwo process compatibility tests that any integratableprocess had to meet:We measured the etch rate of (NH4)2Sx onInAIAs, InGaAs and GaAs. InGaAs and GaAsexhibited minimal etchA/hr). InAlAs was etchedA/hr. These results areintegration.rates (less than 10at a rate of about 100adequate for processWe established that the S treatment is compat-ible with conventional photolithography. Nopattern degradation or adhesion difficultieswere observed after (NH4) 2Sx treatment of aphotoresist patterned wafer.Following these process compatibility tests, wecarried out an additional test to select the properchemical treatment prior to (NH4) 2Sx application. Wefabricated Van der Pauw structures in typicalInAIAs/InGaAs MODFET heterostructures. Thesestructures were subject to several pretreatments assummarized in table 1. In all cases, a selectivesuccinic-acid based gate recess was performed justprior to S treatment as this is a key constrain in theprocess. In addition to a reference sample withoutS treatment, four different pretreatment processeswere examined, as listed in table 1. The sheetcarrier concentration before and after S passivationwas measured for all samples.The results summarized in table 1 indicate that theomission of a pretreatment before (NH 4)2 Sx applica-tion resulted in the maximum change in the sheetcarrier concentration (with respect to the referencesample) as a result of S passivation. The otherapproaches were much less effective. From aprocess integration point of view, this is also afavorable alternative because of its simplicity. Inconsequence we decided not to perform any pre-treatment between succinic acid selective etchingand (NH4) 2Sx application.2.3 S-passivated InAIAs/InGaAsMODFETsHaving selected the process parameters of the Streatment, we proceeded to carry out a completefabrication run of InAIAs/InGaAs MODFETs. Thestarting heterostructure is shown in figure 1. Thisheterostructure was designed in collaboration withRaytheon Research Division, and it wasMBE-grown at Raytheon by Bill Hoke. This designincorporates a number of features that are targetedfor power applications. First, it is a double-5 M.S. Carpenter, M.R. Melloch, and T.E. Dungan, "Schottky Barrier Formation on NH4S-treated N- and P-type (100) GaAs," App.Phys. Lett. 53(1): 66-68 (1988); J. Fan, H. Oigawa, and Y. Nannichi, "Metal-dependent S-barrier Height with the (NH 4)2S,-treatedGaAs," Jap. J. App. Phys. 27(11): L2125-2127 (1988).6 N. Yoshida, M. Totsuka, J. Ino, and S. Matsumoto, "Surface Passivation of InAIAs using (NH4)2S, and P2SJNH,S," Jap. J. App. Phys.33(3A) part 1:1248 (1994).30 RLE Progress Report Number 137Chapter 2. Heterostructure Field-Effect TransistorsTable 1. Summary of process and sheet charge concentration results in five samples as a function of the chemicaltreatment applied prior to S passivation.heterostructure with doping above and below thechannel. Second, we used delta-doping on bothlayers. Third, we incorporated a thin undoped capthat is to be selectively etched. Our insulator isthicker than usual, 300 A, in order to obtain a highbreakdown voltage. The channel is thick so as toget high transconductance and low outputconductance and therefore high gain.Our process is standard. We use SiNx-assistedliftoff for all our metal layers with the exception ofthe pads which are performed using chlorobenzene.The ohmic contacts are made by rapid-thermallyannealing a AuGe bilayer. Before S treatment andgate evaporation, we perform selective mesasidewall recessing to eliminate a very deleterious70 A300 APtfTi/AuAuGeIn.53Ga.47AsIn.52AI.48As- i.... S . . ........... , 3 0 A ....................................................................In.s3Ga.47As8-Si ' . . . . ..0 AIn.52AI.48As2550 A200 AFigure 1. Schematic cross-section of fabricated modulation-doped field-effect transistor. Theat Raytheon Research Division by Bill Hoke.heterostructure was grownSemico Clean 5% NH 40H Dilute H2 SO4 :H20 2Pre-Treatment(NH4) 2Sx Treatment - 10 min. 10 min. 10 min. 10 min.Relative change in - 2% - 16% - 6% - 5% - 3%sheet concentrationChapter 2. Heterostructure Field-Effect Transistorsleakage path between the gate and the channel.7For this we use a succinic acid solution. This simul-taneously etches in a selective way the InGaAs capin the intrinsic portion of the device exposing theInAlAs insulator. The sample was cleaved at thispoint into two pieces. One half underwent the Streatment presented in the previous section. Thesecond half was a reference sample that followed aconventional 5 percent NH 40H pre-gate treatment.Both halves were joined again for gate evaporation.This consisted of a Pt/Ti/Au stack. The process fin-ished with the evaporation and lift-off of Ti/Au pads.Devices with gate lengths 0.8 pm long and 50 pmwide have been tested. Typical output character-istics of a S-treated device are shown in figure 2.Qualitatively, they do not differ much from theuntreated devices. A summary of average values ofimportant figures of merit for both technologies islisted in table 2. Mean values for the maximumcurrent that these devices can handle are 450 and475 mA/mm, for the S-treated and untreateddevices respectively. A plot of transconductanceand drain current versus VGs is shown in figure 3for different values of VDS. The average peaktransconductance of the S-treated devices is 440mS/mm. This contrasts with an average value of380 mS/mm for the reference devices. This signif-icant improvement in gm could be explained by aslight etching of the InAIAs insulator or by the elimi-nation of a surface oxide that is unavoidablypresent between the gate and the InAIAs insulatorin conventional processing. In fact, the thresholdvoltage has shifted slightly from -0.7 V to -0.55 V asa result of the treatment.Sample ID No Sulfur Sulfur(VT) -0.7 V -0.55 V(gm-ak) 380 mS/mm 440 mS/mm(IDss) 475 mA/mm 450 mA/mm(BVDs) 7.5 V 8.3 VTable 2. Summary of MODFET results for S-treated andreference devices with L = 0.8 pm and W, = 50 pm.Figure 2. Output characteristics of a S-treated L, = 0.8pm, W, = 50 pm MODFET.Figure 3. Plot of transconductance and drain current vs.VGs for a S-treated L, = 0.8 pm, Wg = 50 pm MODFETfor three values of VDS-In spite of this, the breakdown voltage of thesedevices is excellent. We have measured anaverage off-state three-terminal breakdown voltageof 7.5 V in the conventional device (defined at acurrent of 1 mA/mm). For the S-treated device, thisvalue improved to 8.3 V. Figure 4 shows a plot ofthe drain-current injection technique8 applied to aS-treated device. A three-terminal breakdownvoltage in excess of 8 V is obtained.7 S.R. Bahl and J.A. del Alamo, "Elimination of Mesa-Sidewall Gate-Leakage in InAIAs/InGaAs Heterostructures by Selective SidewallRecessing," IEEE Electron Dev. Lett. 13(4): 195-197 (1992).8 S.R. Bahl and J.A. del Alamo, "A New Drain-Current Injection Technique for the Measurement of Breakdown Voltage in FETs," IEEETrans. Electron Dev. 40(8): 1558-1560 (1993).32 RLE Progress Report Number 137Eoo300 E(IE200 EM-1.0 -0.5 0.0 0.5 1 0 1.5VGS (V)Figure 4. Plot of VDs and Is versus VGs for ID =for a S-treated L = 0.8 pm, W, = 50 pmshowing a three-terminal breakdown voltage in8 V.1 mA/mmMODFETexcess ofA detailed analysis of the impact of S passivation iscurrently under way. Our preliminary results indicatethat S passivation improves the transconductanceand the breakdown voltage of the device while itslightly degrades the maximum current drivability. Inthe near future, we will carry out detailed C-V char-acteristics of gate diodes so as to understand thecharge control in the intrinsic portion of the device.We will also measure high-frequency S-parameters.Moolji, A.A., S.R. Bahl, and J.A. del"Impact Ionization in InAIAs/InGaAsIEEE Electron Dev. Lett. 15(8): 313-315Alamo.HFETs."(1994).ThesesAdams, T. Gate Delay in InP Heterostructure Field-Effect Transistors. B.S. thesis. Dept. of Electr.Eng. and Comput. Sci., MIT, 1994.Reiner, J.W. A Small-Signal Model for SurfaceEffects in InAIAs/lnGaAs HFETs. B.S. thesis.Dept. of Electr. Eng. and Comput. Sci., MIT,1994.-1.0oEIn -0 4 -.- -0> .Wo (0.0.3 -2 1 0VGS (V)Chapter 2. Heterostructure Field-Effect Transistors2.4 Publications and ConferencePapersBahl, S.R., and J.A. del Alamo. "Physics of Break-down in InAIAs/n*-InGaAs Heterostructure Field-Effect Transistors." IEEE Trans. Electron Dev.41(12): 2268-2275 (1994).Berthold, G., M. Mastrapasqua, C. Canali, M.Manfredi, E. Zanoni, S.R. Bahl, and J.A. delAlamo. "Electron and Hole Real Space Transferin InAIAs/InGaAs Heterostructure Device." Pro-ceedings of the 24th European Solid StateDevice Research Conference. Eds. C. Hill andP. Ashburn. Editions Frontieres. Edinburgh,United Kingdom, September 11-15, 1994. pp.631-634.Berthold, G., E. Zanoni, M. Manfredi, M. Pavesi, C.Canali, J.A. del Alamo, and S.R. Bahl."Electroluminescence and Gate Current Compo-nents of InAIAs/InGaAs HFETs." 52nd AnnualDevice Research Conference, Boulder,Colorado, June 20-22, 1994.From left: graduate student Jody L. House, Professor Leslie A. Kolodziejski, and graduate student Kuo-YiLim (Photo by John F. Cook)34 RLE Progress Report Number 137

Physics of InAIAs/InGaAs Heterostructure Field-Effect Transistors

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Physics of InAIAs/InGaAs Heterostructure Field-Effect Transistors

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