Contains reports on one research project.National Institutes of Health (Grant 5 P01 GI114940-05)Joint Services Electronics Programs (U.S. Army, U. S. Navy, and U. S. Air Force) under Contract DAAB07-71-C-030

Allen, Jonathan

Jensen, E. R.

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XI. COGNITIVE INFORMATION PROCESSINGProf. M. EdenProf. J. AllenProf. B. A. BlesserProf. T. S. HuangProf. F. F. LeeProf. S. J. MasonProf. W. F. SchreiberB. S. BarbayJ. BonnW. T. BorrozJ. E. BowieB. E. BoyleP. CoueignouxJ. R. Ellis, Jr.I. S. EnglanderA. AI. FakhrA. E. FilipS. G. FinnW. B. GrossmanD. W. HartmanAcademic and Research StaffProf. D. E. TroxelProf. I. T. YoungDr. R. R. ArcherDr. G. H. GranlundDr. E, G. GuttmannDr. L. P. A. HenckelsDr. K. R. InghamDr. J. I. MakhoulGraduate StudentsM. HubelbankF. H. IvesJ. W. KlovstadH. S. MagnuskiL. A. MarksP. L. MillerB. AlinkowO. R. Mitchell, Jr.J. A. MyersD. O'ShaughnessyR. A. PiankianG. PoonenR. S. PutnamR. San AntonioDr. D. M. OzonoffDr. O. J. TretiakF. X. CarrollDeborah A. FinkelE. R. JensenJ. W. ModestinoJ. S. VenturaR. J. Shillman1). G. SitlerJ. R. SloanA. A. SmithR. I). SolomonM. SporerJ. H. StahlerW. D. StrattonH-m. D. ToongK. P. WacksY. D. WillemsH. M. WolfsonK. HI. YungA. NEW HIGH-SPEED MULTIPLIER DESIGNWith the advent of MSI and LSI integrated circuit technology, there is no doubt thatdigital multipliers of very high speed can be achieved, once it is agreed what shouldbe incorporated in these chips.l In the meantime, we can achieve a very fast design bysimultaneously exploiting the mathematical structure of binary two's-complement mul-tiplication and existing AISI circuits which can be adapted in a natural way to the struc-ture of this task. Accordingly, we shall show that the expression for binary multiplicationcan be rewritten to suggest use of the 74181 Arithmetic Logic Unit (ALU) in a straight-forward way that achieves high speed, simple layout, and very little logic external tothe ALU array.In order to display the desired structure of multiplication, we shall consider themultiplication of two 4-bit two's-complement numbers. Let each such number be repre-sented asThis work was supported by the National Institutes of Health (Grant 5 P01GI114940-05), and by the Joint Services Electronics Programs (U.S. Army, U.S.Navy, and U. S. Air Force) under Contract DAAB07-71-C-0300).QPR No. 105 147(XI. COGNITIVE INFORMATION PROCESSING)Z - z 3 z 2 zlz 0 = -23z + 22z2 + 21z1 + 20 zo'where each z. is either 1 or 0, so that the product of two such numbers is1XY = 2 6x 3 Y3 - 25(x 3 Y2 +x 2 Y3 ) + 24 (-x 3Yl+x2 Y2 -x 1Y 3 )+ 2 3(-X3Yo+x 2 Y +x 1Y 2 -XoY3 )+ 22(x 2 yo+xY +xo Y2)+ 21 (X1Yo+ X oY 1 )+ 20xoyThis sum is commonly arranged in an array in which each column contains factors oflike powers of 2, as in Fig. XI-1. The factors can be further rearranged, as-x 3Y 0 + x 2Y0 + x 1y 0 + x 0-x3 1 + x2 Y1 + xlY1 + x 0Y 1-x3Y 2 + x 2Y2 + xlY 2 + x0Y Z+x3Y 3 - x2y 3 - x 1 3 - x0Y 3Fig. XI-1. Array representation of two's -complement multiplication.x2Y0  x 1Y 0  x0o 0x2Y1 xlY1  x 1x2 2  x 1 2  x 0 Y2x3Y 3x 3Y2  x3y1  x3 y 3x2 Y 3  x 1Y 3  x0Y 3Fig. XI-2. Multiplication array, grouped in positive and negative terms.QPR No. 105 148(XI. COGNITIVE INFORMATION PROCESSING)shown in Fig. XI-2, in order to group positive and negative terms. At this stage, eachrow has a constant factor for each term such as yo for the top row, and these can befactored out as bits that control the conditional inclusion of a given row in the final sum.Thus, in Fig. XI-3, the top row (x 2 x 1 x o ) will be added into the sum just in caseYo = 1, and similarly for the other rows. Figure XI-3 also shows 6 conditionalterms to be summed, but one of these, x 3Y3 , affects only the most significant bitposition. If this term is included in any other row (say, row 6), the only changeNUMBER CONDITIONx 2  x I  xOx 2  x I  xOx2  x I  xO Y2x3  Y3. Y2 Yl YO ×3x2 XI XO Y3Multiplicationcontrol bits.array, grouped by rows and their respective(((A + B) + C) - (D + E))Fig. XI-4. Illustrating the parallel nature of the multiplication task.QPR No. 105Fig. XI-3.-- t 0t3-- - t 1'R\149(XI. COGNITIVE INFORMATION PROCESSING)in the final result might be a carry out of the most significant bit. When sign exten-sion is not desired, it is thus possible to incorporate the x 3 Y3 term in row 6, andwe are left with just 5 rows to sum. It is this representation of the product as asum of conditional terms that can be exploited by the ALU design.Having rewritten the product as a sum of terms, each conditioned on a controlbit, the next step is to minimize the sum-and-carry delays by exploiting the inher-ent parallelism of the array. Referring to the five rows as A through E, Fig. XI-4shows how a tree structure permits simultaneous sums to be computed, rather thanperforming each indicated sum in serial, left-to-right order. In Fig. XI-4, eachbox denotes an ALU adder, and we assume that each add is completed in A seconds.During the first A seconds two adds are completed, followed by one add in each ofthe two succeeding intervals. There are two advantages in this scheme. First,the total delay would be 4A seconds if the adds were done serially, but when theparallelism is utilized, only 3A seconds of delay result. More generally, for largersized numbers N bits long, a similar binary tree would lead to (log 2 N)A secondsdelay, whereas a serial procedure would require (N-1)A seconds delay. For N =16, the saving is A(15-4) = llA, a very substantial figure. When N is not a powerof 2, some branches of the full binary tree are pruned, but the saving in timebecause of parallelism is still obtained. The second advantage is that the binarytree arrangement can be implemented in a straightforward and natural way by usingthe 74181 ALU, 24-pin ISI package.The 74181 ALU, shown in Fig. XI-5, operates on two 4-bit inputs in a mannerprescribed by the four control bits, So through S3 , and the Mode Control bit MI, toproduce a single 4-bit output. As shown in Fig. XI-6, all of the needed controlfunctions can be realized by appropriate use of So through S 3 , MI, and C , the lastbeing the input carry to the least significant bit. Note that only the double condi-tional sum, (A if z) + (B if y), requires extra circuitry to translate the conditionbits (z and y) into ALU controls, but that this circuitry is very simple, containingonly an XOR gate and an inverter.Figure XI-7 shows the complete design for a 4 X 4 multiplier, in which the con-trol circuitry is shown in detail. Depending on the size of the multiplier desired,extra time savings may be realized by appropriate partitioning of the array andinsertion of carries, but the basic details remain the same. The authors havedesigned 16 X 16 and 16 X 24 arrays, which illustrate further refinements. Thesedesigns are available to the interested reader.A further advantage of the ALU is its wide availability. Originally, it wasintroduced in TTL, but Schottky TTL and MECL 10,000 versions are now avail-able. Worst-case multiplication times will depend on which one of these pack-ages is used, but a 16 X 16 design should yield a completion time of 95-100 nsQPR No. 105 150Fig. XI-5. Logic diagram for the 74181 Arithmetic Logic Unit.BASICFUNCTIONCONTROL SIGNALSS1 2 S3 M0 1 1 0 0 1 xA 0 0 0 0 0 1B 0 1 0 1 1 xA+B 1 0 0 1 0 1A-B 0 1 1 0 0 0CONTROLFUNCTIONA+BA- BA+(B if y)(A if z)+(B if y)I0yZE0yFig. XI-6. Control functions for the 74181 Arithmetic Logic Unit.QPR No. 105 151(XI. COGNITIVE INFORMATION PROCESSING)74181 CONTROL( y0 0 x2  x I  x0I 1 I I 174181 CON TROL y2T5  T4  T30 x3  Y2 x2 Y1 X Y0 x074181 CONTROL x32-0 5 T4 T374181S 6  S5  4  S3 S2  S1  SO(a)3 So ,S3 2S1 M 1 y73CONTROLS 0, 2 CONTROL 1(b)Fig. XI-7. Four by four multiplier block diagram, with externalcontrol circuitry.in Schottky TTL. This is considerably faster than the performance obtainable fromspecialized multiplier packages, such as the Fairchild 9344 or the Advanced MicroDevices AM 2505. Since the ALU package has many uses, it is relatively inexpensive,particularly considering the resulting multiplier speed. The package count, and hencepower, is high (approximately N(N+1)/4 for an NXN multiply; for N= 16,69 ALU's wererequired) but layout is simple, and no other design incorporating standard commercialMSI packages has been able to yield the speed of this ALU array.Certainly faster or cheaper multipliers have been built. The ALU in a binary tree,however, appears to be an optimal choice when very high speed is desired from standardcommercial packages.J. Allen, E. R. JensenReferences1. S. D. Pezaris, "A 40-ns 17-bit by 17-bit Array Multiplier," IEEE Trans. on Com-puters, Vol. C-20, No. 4, pp. 442-447, April 1971.QPR No. 105 152

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