Contains reports on two research projects.Lincoln Laboratory, Purchase Order DDL-B222U.S. Air Force under Air Force Contract AF19(604)-520

Leeson, D. B.

Sussenguth, E. H.

Weinreb, S.

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XVII. CIRCUIT THEORYProf. S. J. Mason Prof. R. D. Thornton B. J. LeonProf. H. J. Zimmermann J. T. Andreika T. G. Stockham, Jr.Prof. J. Granlund D. G. Kocher E. H. SussenguthProf. C. L. Searle D. B. Leeson S. WeinrebA. NONLINEAR REACTANCE FREQUENCY MULTIPLIERSWe have completed a circuit analysis of an Nth-order frequency multiplier using anonlinear reactance in the circuit configurations previously reported (1). A papergiving the details of this analysis has been prepared and submitted for publication.The analysis given in this paper spec-ifies impedence levels, conditions forSoptimum efficiency, and the value of opti-QH 0100,000 mum efficiency for a given lossy nonlinear0 - Q2500 reactance and for given lossy tuned cir-cuits. Figure XVII-1 shows the theoreti-20o - cal optimum efficiency that can be obtained0 Fo='0 0  by using a lossy abrupt-junction nonlinear3o capacitor as a frequency multiplier. QFis the reciprocal of the sum of reciprocal40 Q's of the nonlinear capacitor and linearinductors evaluated at the fundamental2 3 4 5 6 7 8 9 10 frequency. QH is the identical quantityN Nt hHARMONIC ORDER evaluated at the Nth harmonic frequency.Fig. XVII-1. Calculated efficiency versus We have assumed that the nonlinear capac-harmonic order itor does not conduct during any part ofthe cycle.Briefly, the analysis begins with a Taylor-series expansion of the nonlinear charge-voltage relation in the case of a nonlinear capacitor, or flux linkage-current relation inthe case of a nonlinear inductor. Fourier-series expressions for the variables aresubstituted in this Taylor-series expansion and components at identical frequencies areequated. This procedure results in algebraic equations relating Fourier charge coef-ficients to voltage coefficients. With the addition of circuit constraints and small-signalapproximations the analysis is complete.The results of this analysis have been applied in detail to the case of the semicon-ductor nonlinear capacitor. Experimental measurements of input impedance and effi-ciency of frequency doublers containing abrupt-junction nonlinear capacitors haveThis research was supported in part by Purchase Order DDL-B222 with LincolnLaboratory, a center for research operated by M. I. T., which is supported by theU.S. Air Force under Air Force Contract AF19(604)-5200.200(XVII. CIRCUIT THEORY)been made, and good agreement between experiment and theory has been obtained. Itis evident that these devices make highly efficient frequency doublers. Efficiencies of1 db (1.5 mc to 3.0 mc) and 2. 3 db (100 mc to 200 mc) have been measured. A methodof obtaining efficient high-order multiplication is to cascade doublers. By using thismethod an octupler (2 mc to 16 mc) with an efficiency of 6. 5 db has been constructed.D. B. Leeson, S. WeinrebReferences1. D. B. Leeson and S. Weinreb, Frequency multiplication with nonlinear capacitors,Quarterly Progress Report No. 53, April 15, 1959, p. 203.B. A NUMERICAL METHOD FOR COMPUTING POLE AND ZERO LOCATIONSMethods for determining the pole-zero pattern associated with a given magnitude-phase specification are discussed in almost all textbooks on network synthesis. Thesemethods employ tedious analytical calculations or approximate graphical techniques. Amethod of using the principle of analytic continuation, in which an electronic computerperforms all of the calculations and decisions, has been investigated.The procedure applies the Cauchy-Riemann conditions of analyticity to the data,which are prescribed along a vertical line in the complex plane, and determines thevalues of magnitude and phase along a second line close to the first. The second line isthen used to determine a third, the third a fourth, and so on until a pole or zero isreached. Poles and zeros are located by examining the relative magnitudes at thevarious mesh points. For each point, the ratio of the magnitude at that point to thepreceding point is formed and, if at some point the ratio exceeds two and at the nextpoint is less than one-half, we know that a pole lies between the two points. The influ-ence of this pole is then "subtracted" from the orignal data and the computation begunanew. By repeating this process a sufficient number of times a system of poles andzeros is built up that approximates the original specification.This technique has been programmed on the IBM 704 computer, at the M. I. T.Computation Center, with only moderate success. The poles and zeros of elementaryspecifications are located accurately, but in more realistic specifications a build-up oferror in the neighborhood of prospective poles distorts the values so much so that theratio criterion will not locate the pole. (The ratio criterion was derived under theassumption that the true values of the function were available.) Various smoothing andaveraging techniques that were employed to counteract the error were not satisfactory.E. H. Sussenguth201

Circuit Theory

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Circuit Theory

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