Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 145-149).by Andrew Shaw.Ph.D

Shaw, Andrew, 1968-

Shared-memory symmetric multiprocessors (SMP&apos;s) based on conventional microprocessors are by far the most common parallel architecture today, and will continue to be so for the forseeable future. This thesis describes techniques to compile and schedule Id-S, a dialect of the implicitly parallel language Id, for execution on SMP&apos;s. We show that previous implementations of Id for conventional microprocessors incurred an overhead of at least 40-300% over an efficient sequential implementation of Id-S. We break down this overhead into various presence-tag checking and scheduling overheads. Given this overhead, we conclude that a fine-grained, element-wise synchronizing implementation of Id is not suitable for use on small-scale SMP&apos;s. We then describe a parallelization technique for Id-S that discovers both DAG and loop parallelism. Our parallelization exploits Id-S&apos;s single-assignment semantics for data structures. We show that for many programs, our technique can discover ample paralleli..

Andrew Shaw

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Compiling for Parallel Multithreaded Computation on Symmetric Multiprocessors

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Compiling for parallel multithreaded computation on symmetric multiprocessors

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Compiling for parallel multithreaded computation on symmetric multiprocessors

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