Design och implementering av en asynkron pipelinad FFT processor

Abstract

FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that implements the SDF (Single Delay Feedback) radix-22 algorithm. The goal of this report is to outline the knowledge gained during the master's thesis project, to describe a design methodology and to document the different building blocks needed in these kinds of systems