Standard-Cell-library-based design
ow is widely followed in the Application Specific
Integrated Circuit(ASIC) industry. Most of the realistic cell libraries are geometrically
spaced introducing significant sparseness in the library. This is because uniformly
spaced gate sizes would result in a large number of gate sizes and maintaining the
huge volume of data for this number of gate sizes is difficult. This thesis aims to
propose a practical approach to implement integer gate sizes. A parameterized cell
(p-cell) approach to the generation of layouts of standard gates is presented. The use
of constant delay model for gate delay estimation is proposed which eliminates the
need for maintaining huge volumes of delay tables in the standard cell library. This
approach has tremendous potential since it greatly simplifies the standard-cell-based
design methodology and can give significant power and area savings.Power and area
savings of up to 28% are possible using this approach
