A highly integrated CMOS image sensor architecture for low voltage applications with deep submicron process

Abstract

In this paper, a design methodology to fabricate a CMOS imaging system in an ultra-low voltage environment with a deep submicron process is presented. The new design methodology is based on a rail-to-rail pixel architecture together with a high dynamic range single-slope analog-to-digital converter (ADC). Correlated doubling sampling (CDS) is built-in in the readout system to suppress both fix pattern noise and kTC noise. An imaging test chip has been fabricated with a TSMC 0.25μm CMOS process and proved to function at a supply voltage of 1V or below. Two operation modes are also implemented to tradeoff between high speed and low power operations