In the age of high-speed digital circuitry, there exists a need for clean, precise clock signals. In generating and distributing clock signals throughout a circuit, unwanted jitter can become a serious issue. A common technique for attenuating jitter uses phase-locked-loops to treat the signal, but as the clock frequency increases, so does the cost and complexity of the designs. Following the research completed by Dr. Tina Smilkstein [1], this project examines a purely feed-forward technique for attenuating jitter that is low-complexity and robust, and aims to design an integrated circuit that implements the technique
