This paper presents an IF chain suitable for Low-IF fully-integrated GFSK receivers. The circuit performs amplification and channel selection (including image rejection). A five-pole Gm-C polyphase filter forms the core of the IF strip. The filter is current driven and has transimpedance gain of ≃ 120 kΩ. The filter is architectured so that GFSK signals with dynamic range exceeding 50dB can be decoded without the need of any automatic gain control. This AGC-less IF strip was fabricated in standard 0.25 µm CMOS process. It draws 6.2 mA from a 2.5 V supply and has better than 4.8 nA rms input referred noise. Input signals (compliant with Bluetooth) were applied and the output signal was collected for  software decoding . Generated BER plots meet Bluetooth specifications

Boccuzzi, Vito

Glas, Jack

Palaskas, George

Prodanov, Vladimir I.

English

DigitalCommons@CalPoly

A CMOS AGC-less IF Strip for Bluetooth Vladimir Prodanov, George Palaskas, Jack Glas and Vito Boccuzzi Agere Systems,600 Mountain Ave, Murray Hill, NJ 07974, USA Abstract This paper presents an IF chain suitable for Low-IF fully-integrated GFSK receivers. The circuit performs am­pliﬁcation and channel selection (including image rejec­tion). A ﬁve-pole Gm-C polyphase ﬁlter forms the core of the IF strip. The ﬁlter is current driven and has tran­�� simpedance gain of 120 k . The ﬁlter is architectured so that GFSK signals with dynamic range exceeding � � � � can be decoded without the need of any automatic gain control. This AGC-less IF strip was fabricated in stan­dard 0.25 � m CMOS process. It draws 6.2 mA from a 2.5 V supply and has better than 4.8 nA rms input referred noise. Input signals (compliant with Bluetooth) were ap­plied and the output signal was collected for ”software decoding”. Generated BER plots meet Bluetooth speciﬁ­cations. 1. Receiver Topology In this paper we will discuss the implementation of an IF chain for a fully integrated Bluetooth receiver. There are three receiver architectures that are amenable to full integration: direct conversion, single low-IF down-conversion and poly-phase ﬁltering, and wideband-IF double down-conversion (Weaver architecture). The Blue-tooth signal is approximately 1MHz wide with most of its energy concentrated in the middle of the band. Thus, di­rect conversion receiver would be difﬁcult to implement, especially in CMOS because of 1/f noise. The Bluetooth standard has a relaxed image requirement; therefore, a low-IF architecture seems to be the best choice [1]. The selection of the IF is a trade-off between the 1/f noise and the ﬁlter quality factor. We have selected an IF of 2MHz. It gives good ”immunity” to 1/f noise and dc off­sets, while the required � factors are still practical ( � � � ). To perform channel selection a 5-pole active poly-phase ﬁlter was deemed necessary and an image rejection better than 30 � � was sought; this number is easily achievable without resorting to complicated I/Q-mismatch correcting schemes. Since the amplitude of the signal carries no in­formation (GFSK modulation), no harm is done if the ﬁl­ter I/Q outputs are limited. The ﬁnal data detection is done in a differential FM detector. For successful decoding of a Bluetooth signal, our decoder circuit [2] calls for an SNR of about 15 dB, and SDR of 11 dB or better. � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 2. Topology of the IF Strip The core of the IF strip is a 5-th order Butterworth polyphase ﬁlter. In this section we will decide upon the architecture of this ﬁlter, its gain distribution, as well as the interface between the ﬁlter and the I/Q mixers. 2.1. Architecture The most power-efﬁcient way of reducing the ﬁlter’s input referred noise is to implement it as a chain of al­ternating ﬁlter/gain sections. When properly done, the in­put referred noise contribution of successive ﬁlter sections will be reduced. Each section implements a single ”com­plex pole”. We decided upon a ”plain” Gm-C implemen­tation with no internal nodes, because of the high quality �factors of the poles ( � � � � � � ). Due to the high � ’s the parasitic poles of the integrators should be located above 400 MHz. The topology of a complex pole section is shown in Fig 1. Transconductor � � � performs V-I conversion, while the rest of the circuit forms a “complex impedance”,� � . The transconductance of � � � can be adjusted to achieve the desired gain. The overall ﬁlter is a cascade of 5 stages like the one in Fig. 1, and it be can regarded as a ”complex transimpedance” driven by a � � element. The input transconductor and the load of the mixer form a current ampliﬁer. The sole purpose of this ampli­ﬁer is to ”align” the compression point of the ﬁlter tran­simpedance with that of the mixer. We disposed of this current ampliﬁer by co-designing the mixer and the ﬁlter, and injected the output current of the Gilbert-type mixer directly into the ﬁlter transimpedance stage. Portion of the blocker-induced current is shunted to ground through the ﬁlter capacitors of the ﬁrst node. Thus, the blocker is ﬁltered somewhat before it gets a chance to develop a voltage and produce distortion. This gives a 10 dB im­provement in the � � at no extra cost (a similar principle is presented in [3]). In order to avoid loading of the ﬁl­ter, it might be necessary to inject the input current via a folded cascode. 2.2. Stage Ordering and Gain Distribution Since sections implementing higher � ’s are noisier, we placed the ﬁlter sections in ascending order with respect to their � ’s. Transconductance values relative to one an­other are determined as follows. Those setting the real part of the ﬁrst three complex poles, � in Fig. 1, were � � assumed unity, while the � ’s of the last two, high � ,� � poles were taken 1/4 to conserve power. The transconduc­tors that determine the imaginary part of the poles, � � � in Fig. 1, were calculated from the corresponding � ’s � � and the desired � ’s. The transconductors that determine the gains, � � � ’s, are set so that the worst case blocker de­velops the same voltage swings across the ﬁrst three nodes of the ﬁlter. No gain was applied in the last two stages to conserve power. When propagating through the ﬁlter chain the in-band, desired, signal will be ampliﬁed. With this gain distribution, strong in-channel signals will cause compression in the ﬁlter. If we are to keep the chain lin­ear we would have to apply some type of AGC-ing. As discussed in the preceding section the signals coming out of the poly-phase ﬁlter are intentionally limited before de­coding. Naturally, one wonders whether or not it is pos­sible to limit earlier, inside the ﬁlter, and still extract de-codable signal. This question will be answered in the next subsection. 2.3. Soft-Limiting in Presence of a Blocker Consider a soft limiter, a circuit that is linear up to an input signal of � � � � and saturates for larger signals. A blocker with magnitude � � � � is applied to its input. For this signal alone the circuit is perfectly linear. Now, if a desired signal having large dynamic range is added to the input, the soft limiter becomes highly non-linear. In­termodulation tones are produced. Some of these spuri­ous responses would fall on top of the desired signal and even if ﬁltering is applied they can not be removed. If the strength of this interference, however, is sufﬁciently small compared to that of the desired signal, decoding could still be possible. Analysis and simulation show that the minimum signal-to-interference ratio is about 16 dB with the only requirement that the blocker alone does not over­load the soft limiter. This minimum signal-to-interference value is observed when the magnitude of the desired sig­nal is approximately ��� � � � . The signal-to-interference ratio improves fast around this minimum. Due to space limitations the detailed analysis will not be presented here. Limiting of the output current of the gain transconduc­tors, � � � in Fig. 1, would make these circuits behave as soft limiters. Assume that the maximum current, when � �� � � clips, does not overload the impedance it drives, � � � � � � �(a)�� � � � �� � � � � � � � � ���(b)��� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� � � � � � � � � � � � � � in Fig. 1. Then, the voltages that will develop, � � and � � , will have a signal-to-interference of at least 16 dB. At the same time the ﬁltering operation that this stage per­forms remains unaltered. It can be shown that the mini­mum signal-to-interference ratio at the output of the over­all ﬁlter will be about the same, 16 dB, which is good enough at least for decoding of a Bluetooth signal. This was veriﬁed with matlab simulations. Because we were not able to ﬁnd a sufﬁciently robust circuit technique to implement the desired current limit­� �ing, we opted for voltage limiting. In parallel to in Fig. 1 we placed a non-linear conductance, such as back­to-back diodes or a MOSFET, biased so that it would con­duct heavily whenever the voltage swing exceeds certain level. This level is chosen slightly lower than the linear range of the transconductors used. Using voltage clipping instead of current clipping, gives rise to an undesired effect. For certain input lev­els, the nonlinear operation of the circuit causes distortion similar to intersymbol interference, which is particularly pronounced for fast (0,1,0,1,...) data sequences. This dis­tortion causes the Bit Error Rate to increase. However, by using FM demodulation with post-correction [2], the circuit still meets the required speciﬁcations, see Sec. 4. 3. Circuit Implementation In this section we will discuss the transconductor used and the common-mode feedback approach. 3.1. The Transconductor Since in this design we are dealing with the implemen­tation of high Q poles, a transconductor with virtually no parasitic poles is needed. The simplest such transconduc­tor is the MOS differential pair. Linearization is helpful only if it results in larger dynamic range (with respect to simple diff. pair) with the same power dissipation and no frequency degradation. There are very few such transcon­ductors and one of them is shown in Fig. 2(b). This cir­cuit is derived from the stacked-transistor diff. pair shown in Fig.2(a) by splitting the bottom transistor in two and cross-connecting the gates, in a way similar to [4]. The regular diff. pair and the new circuit have exactly the same power consumption and output current noise. The cross-connection trades transconductance for larger input linear range. The DR of the new circuit is improved because M7 M1 M2 M6 M5 M8 M3 M4 (a) � � � � � � � � � � � � � � � � � � � � � � � � �� � � � � � �� �� � (b) M1 M2 M6 M10 M9M4 M5 M8 M7 M3 M11 � � � � �� �� � � � � � � �� � ���� �� �� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � the percent increase in input linear range is larger than the percent decrease in transconductance value. 3.2. The CMFB Circuit The common-mode feedback circuit we used is shown in Fig. 3(a). The common-mode voltage at the output of transconductor � � � � � is sensed at the common-source node, S, of an identical transconductor � .� � � � � It can be shown that the voltage at node S follows the common-mode component of the voltage at the input of � � � � � � , while it is unaffected by the differential component. In­stead of using an extra transconductor for common-mode sensing, we used transconductors which are already con­nected to the nodes whose common-mode voltage we try to sense. This approach to common-mode voltage sensing has been quite popular recently, see for example [5]. The voltage at the common-source node, � � , is subse­quently fed-back at the gates of M1 and M2 in Fig. 3(a) through a level shifter � .� � The reader can verify that this conﬁguration indeed establishes a negative feedback for the common-mode voltage. The common-mode feed­back loop depicted in Fig. 3(a) has a dominant pole lo­cated at the drains of M1 and M2, which is the only high impedance point in the loop and, moreover, the integrat­ing capacitors are connected there; no frequency compen­sation is therefore needed. Fig. 3(b) shows a scheme that adjusts � so that � � the output common-mode voltage equals certain reference �value, � �� � � � � , over process and temperature variations. This scheme is conceptually similar to the common-mode feedback used in [6]. The desired common-mode volt­� age � � � � � � is applied at the input of a common-mode sensing circuit, identical to the one used in Fig. 3(a). The voltage developed at node S’ is level shifted by � and is � � then applied to the gate of transistor M7. This transistor is matched to the active load of the transconductor. The cur­rent that develops should be identical to the bias current of the transconductor. The corresponding error is ampli­ﬁed by M9 and fed back to the gate of M3 to adjust � ,� � so that the two current are equal. The bias voltage � �� � is used to bias all common-mode feedback circuits in the ﬁlter. The p-MOS accumulation capacitors we used have an accuracy of � over process and temperature. The ﬁl­� � ter transconductors were referenced to an external resis­tor. The achieved accuracy (simulated � � variation) was � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� � � � � � � � � � � � � .The resulting absolute frequency accuracy of the ﬁl­� � ter transfer function was sufﬁcient for our application. 4. Measurement Results This section presents the measured results for the IF chain. The test setup is composed of an off-chip downcon­version mixer which produces the desired I and Q inputs for the ﬁlter, and appropriate ampliﬁcation stages. Fre­quencies above the LO frequency of the mixer are per­ceived as positive, and below it as negative. Since the ﬁlter should be driven by a current, on-chip buffers were included to convert the output voltage of the mixer to an input current. Fig. 4 shows the measured frequency re­sponse of the ﬁlter which closely matches the desired But­terworth response. The measured image rejection is about 45 dB. This number includes contribution from the mixer, which can either improve or deteriorate the image rejection, depend­ing on whether the mismatches of the mixer and the ﬁlter tend to cancel or reinforce each other. The number given above was a worst case measurement, and it is consistent with the expected image rejection from a circuit with a good layout at this frequency. Because of the fairly unconventional architecture em­ployed in the ﬁlter, it was decided to perform BER tests instead of spurious analyses in the spectral domain. A GFSK modulated signal was applied to the ﬁlter together with the appropriate interferers as described in the Blue-tooth speciﬁcations. The output of the ﬁlter was sampled and decoded off-line to estimate the achieved BER. The technique presented in [2] was used to improve the BER of the detected signal. Fig. 6 shows the BER measure­ments corresponding to the Bluetooth tests. For each data point 41 kbits of data were processed. The input signal is swept across the required dynamic range while the block­ers were set to the levels shown on the side of the plots. For each test the upper/lower curve corresponds to BER before/after the post-detection algorithm is applied. The ﬁlter satisﬁes all tests dictated by the Bluetooth standard. Due to space limitations we didn’t show the intermodulation test which is easily passed by virtue of the current-input ﬁltering, the co-channel interference test, and the +3 MHz blocker test, which are also satisﬁed. The input referred noise current of the ﬁlter integrated over the passband is 4.8 nA rms. � � � � � � � � �� � � � � � � � � �� � � �� � � � � � � � � � � � � � � � � � � � � � � � � � ��� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Fig. 5 shows a microphotograph of the fabricated chip. The chip occupies about 0.3 mm � . 5. Conclusion A standard CMOS, 6.2 mA, IF strip for a fully inte­grated GFSK receiver has been presented. The proposed architecture operates in a nonlinear fashion by taking ad­vantage of the angular modulation of the input. Although the circuit uses no Automatic Gain Control the result­ing performance is compliant with the Bluetooth standard speciﬁcations. [1] H. Darabi et al., A 2.4GHz CMOS Transceiver for Bluetooth, IEEE International Solid State Circuit Conference, February 2001, San Fransisco, CA. [2] J. Glas, V. Prodanov, V. Boccuzzi	 A Bluetooth low-IF data detector with post-detection correction, submitted to Globe­com 2001. [3] A. Yoshizawa,	 Y. Tsividis An Anti-Blocker Structure MOSFET-C Filter For a Direct Conversion Receiver, Cus­tom Integrated Circuit Conference, May 2001, San Diego, CA. [4] F. Krummenacher, N. Joel, A 4 MHz CMOS continuous time ﬁlter with on-chip automatic tuning, IEEE Journal of Solid State Circuits, vol. 23, pp. 750-757, June 1988. [5] T. Itakura et al.	 A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C ﬁlter IC, Solid-State Cir­cuits, IEEE Journal of , Volume: 34 Issue: 8 , Aug. 1999, pp 1155-1159. [6] Khorramabadi, H.; Gray, P.	 High-frequency CMOS contin­uous time ﬁlters, IEEE Journal of Solid-State Circuits, Vol­ume: SC-19, No 6 , Dec. 1984, pp 939-948. -3 -2 -1 0 1 2 3 4 5 MHz � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � -3 MHz 12.5 � A -2 MHz 17.7 � A -1 MHz 12.5 � A 0 MHz 89 � A +1 MHz 2.8 � A +4 MHz 89 � A +5 MHz 126 � A 0.9 9 90 input current peak � A� � � � � � � � � � �� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� � � � � � � � � � � � � � � � � � � � � � �� � � � � � �� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� � � � �� � � � � � � � � � � � �� � � � � � � � � � � � � � � � � � � �� � � � � � � � �� � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� � � � � � � � � �� � � � � � � �	 � � � � � � � � � � � � � � � � � � � � � ��� � � � � � � � � � � � � � � � � � �� � �� � � � � 

A CMOS AGC-less IF Strip for Bluetooth

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A CMOS AGC-less IF Strip for Bluetooth

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