This paper describes a formal executable semantics for the Verilog
hardware description language. The goal of our formalization is to provide a
concise and mathematically rigorous reference augmenting the prose of the
official language standard, and ultimately to aid developers of Verilog-based
tools; e.g., simulators, test generators, and verification tools. Our semantics
applies equally well to both synthesizeable and behavioral
designs and is given in a familiar, operational-style within a logic providing
important additional benefits above and beyond static formalization. In
particular, it is executable and searchable so that one can ask
questions about how a, possibly nondeterministic, Verilog program can legally
behave under the formalization. The formalization should not be seen as the
final word on Verilog, but rather as a starting point and basis for community
discussions on the Verilog semantics.CCF-0916893CNS-0720512CCF-0905584CCF-0448501NNL08AA23Cunpublishedis peer reviewe
