An alternative architecture of the L0(æ) processor

Abstract

97-024 An alternative architecture of the L0(µ) processor and its implementation are presented. The architecture of the processor is based on a strong zero­suppression in order to minimize the data flow coming from the muon detector. It can be achieved by the fast identification of the muon tracks in all muon chambers using adequately dimensioned pad sectors and by transferring the individual pad information only for the regions close to the muon tracks. The proposed solution is simple, flexible and compact. Based on present technology the processor could execute the complete L0(µ) algorithm and make its decision available within less than 3 µs