Gray, Paul R

Hurst, Paul

Lewis, Stephen

Meyer, Robert G

CERN Document Server

ANALYSIS AND DESIGNOF ANALOG INTEGRATEDCIRCUITSFourth EditionPAUL R. GRAYUniversity of California, BerkeleyPAUL J . HURSTUniversity of California, DavisSTEPHEN H. LEWISUniversity ofCalifornia, DavisROBERT G. MEYERUniversity of California, BerkeleyJOHN WILEY & SONS, INC.New York /Chichester/Weinheim /Brisbane / Singapore/TorontoContentsCHAPTER 1	1.5 .2 Comparison of Operating RegionsModels for Integrated-Circuit Active of Bipolar and MOS TransistorsDevices 1 45.1 Introduction 11 .5 .3 Decomposition of Gate-Source1 Voltage 471 .2 Depletion Region of a pn Junction 1 1 .5 .4 Threshold Temperature1.2.1 Depletion-Region Capacitance 5 Dependence471.5.5 MOS Device Voltage Limitations1.2 .2 Junction Breakdown 6 481.3 Large-Signal Behavior of Bipolar 1 .6 Small-Signal Models of the MOSTransistors 8 Transistors 491.3 .1 Large-Signal Models in the 1 .6 .1 Transconductance 50Forward-Active Region 9 1 .6 .2 Intrinsic Gate-Source and1 .3.2 Effects of Collector Voltage on Gate-Drain Capacitance 51Large-Signal Characteristics in the 1.6 .3 Input Resistance 52Forward-Active Region 141.3 .3 Saturation and Inverse Active 1.6 .4 Output Resistance 52Regions 16 1 .6 .5 Basic Small-Signal Model of the1 .3 .4 Transistor Breakdown Voltages MOS Transistor 5220 1 .6.6 Body Transconductance 531 .3 .5 Dependence of Transistor Current 1.6 .7 Parasitic Elements in theGain RF on Operating Conditions Small-Signal Model 5423 1.6 .8 MOS Transistor Frequency1.4 Small-Signal Models of Bipolar Response 55Transistors 26 1 .7 Short-Channel Effects in MOS1 .4.1 Transconductance 27 Transistors 581 .4 .2 Base-Charging Capacitance 28 1.7 .1 Velocity Saturation from the1.4 .3 Input Resistance 29 Horizontal Field 591.7.2 Transconductance and Transition1.4 .4 Output Resistance 29 Frequency 631 .4 .5 Basic Small-Signal Model of the 1 .7 .3 Mobility Degradation from theBipolar Transistor 30 Vertical Field 651 .4.6 Collector-Base Resistance 30 1 .8 Weak Inversion in MOS Transistors1 .4.7 Parasitic Elements in the 65Small-Signal Model 311.4 .8 Specification of Transistor 1 .8 .1 Drain Current in Weak InversionFrequency Response 34 661 .8.2 Transconductance and Transition1.5 Large Signal Behavior of Frequency in Weak Inversion 68Metal-Oxide-Semiconductor 1.9 Substrate Current Flow in MOSField-Effect Transistors 38 Transistors 711 .5 .1 Transfer Characteristics of MOSDevices 38A.1 .1 Summary of Active-DeviceParameters 73CHAPTER 2	2.9.1 n-Channel Transistors 131Bipolar, MOS, and BiCMOSIntegrated-Circuit Technology 78 2.9.2 p-Channel Transistors 1412.1 Introduction 78 2.9 .3 Depletion Devices 1422.2 Basic Processes in Integrated-Circuit 2.9.4 Bipolar Transistors 142Fabrication 79 2.10 Passive Components in MOS2.2.1 Electrical Resistivity of Silicon Technology 14479 2.10 .1 Resistors 1442.3 High-Voltage Bipolar 2.14 Economics of Integrated-CircuitIntegrated-Circuit Fabrication 88 Fabrication 154Contents xi2.2.2 Solid-State Diffusion 80 2.10 .2 Capacitors in MOS Technology2.2.3 Electrical Properties of Diffused 145Layers 82 2.10 .3 Latchup in CMOS Technology2.2.4 Photolithography 84 1482.2 .5 Epitaxial Growth 85 2.11 BiCMOS Technology 1502.2.6 Ion Implantation 87 2.12 Heterojunction Bipolar Transistors2.2.7 Local Oxidation 87 1522.2.8 Polysi1icon Deposition 87 2.13 Interconnect Delay 1532.4 Advanced Bipolar Integrated-Circuit 2.14.1 Yield Considerations inIntegrated-Circuit FabricationFabrication 92 1542.5 Active Devices in Bipolar Analog 2.14.2 Cost Considerations inIntegrated Circuits 95 Integrated-Circuit Fabrication2.5 .1 Integrated-Circuit npn Transistor 15796 2.15 Packaging Considerations for2.5.2 Integrated-Circuit pnp Transistors Integrated Circuits 159107 2.15.1 Maximum Power Dissipation 1592.6 Passive Components in Bipolar 2.15.2 Reliability Considerations inIntegrated Circuits 115 Integrated-Circuit Packaging 1622.6 .1 Diffused Resistors 115 A.2.1 SPICE Model-Parameter Files 1632.6.2 Epitaxial and Epitaxial PinchResistors 1192.6.3 Integrated-Circuit Capacitors 120 CHAPTER 3Single-Transistor and Multiple-Transistor2.6.4 Zener Diodes 121 Amplifiers 1702.6 .5 Junction Diodes 122 3.1 Device Model Selection for2.7 Modifications to the Basic Bipolar Approximate Analysis of AnalogProcess 123 Circuits 1712.7 .1 Dielectric Isolation 123 3.2 Two-Port Modeling of Amplifiers 1722.7.2 Compatible Processing for 3.3 Basic Single-Transistor AmplifierHigh-Performance Active Devices Stages 1741242.7.3 High-Performance Passive 3 .3 .1 Common-Emitter ConfigurationComponents 127 1752.8 MOS Integrated-Circuit Fabrication 3 .3 .2 Common-Source Configuration127 1792.9 Active Devices in MOS IntegratedCircuits 1313 .3 .3 Common-Base Configuration 1833 .3 .4 Common-Gate Configuration 186xii Contents3.3 .5	Common-Base and Common-Gate 3.5 .6 .5 Input Offset Current ofConfigurations with Finite ro	188 the Emitter-Coupled Pair3.3.5 .1 Common-Base and 235Common-Gate Input 3.5.6.6 Input Offset Voltage of theResistance 188 Source-Coupled Pair 2363.3 .5 .2 Common-Base and 3.5.6 .7 Offset Voltage of theCommon-Gate Output Source-Coupled Pair: Ap-Resistance 190 proximate Analysis 2363.3.6 Common-Collector Configuration 3 .5.6 .8 Offset Voltage Drift in the(Emitter Follower) 191 Source-Coupled Pair 2383 .3 .7 Common-Drain Configuration 3.5.6 .9 Small-(Source Follower) 195SignalCharacteristics of3 .3 .8 Common-Emitter Amplifier with Unbalanced DifferentialEmitter Degeneration 197 Amplifiers 2383.3.9 Common-Source Amplifier with A.3.1 Elementary Statistics and theSource Degeneration 200 Gaussian Distribution 2463.4 Multiple-Transistor Amplifier Stages202CHAPTER 43.4 .1 The CC-CE, CC-CC, and Current Mirrors, Active Loads, andDarlington Configurations 202 References 2533.4.2 The Cascode Configuration 206 4.1 Introduction 2533.4.2 .1 The Bipolar Cascode 206 4.2 Current Mirrors 2533.4.2.2 The MOS Cascode 2081GlP4.2.eneraroperties 2533.4.3 The Active Cascode 2114,2,2 Simple Current Mirror 2553.4.4 The Super Source Follower 2134.2.2.1 Bipolar 25535 Differential Pairs 215.4.2.2.2 MOS 2573.5 .1 The do Transfer Characteristic of 4.2.3 Simple Current Mirror with Betaan Emitter-Coupled Pair 215 Helper 2603.5.2 The do Transfer Characteristic with 4.2.3 .1 Bipolar 260Emitter Degeneration 2173 .5 .3 The do Transfer Characteristic of a 4.2.3.2 MOS 262Source-Coupled Pair 218 4.2.4 Simple Current Mirror withDegeneration3 .5.4 Introduction to the Small-Signal 262Analysis of Differential Amplifiers 4.2.4 .1 Bipolar 262221 4.2.4.2 MOS 2633 .5 .5 Small-Signal Characteristics of 4.2 .5 Cascode Current Mirror 263Balanced Differential Amplifiers224 4.2.5 .1 Bipolar 2633.5 .6 Device Mismatch Effects in 4252 MOS 266. . .Differential Amplifiers 2313.5.6.1 Input Offset Voltage and 4.2.6 Wilson Current Mirror 274Current 231 4.2.6 .1 Bipolar 2743.5 .6 .2 Input Offset Voltage of 4.2 .6 .2 MOS 277the Emitter-Coupled Pair232 4,3 Active Loads 2783.5 .6 .3 Offset Voltage of the 4.3 .1 Motivation 278Emitter-Coupled Pair : 4.3 .2 Common-Emitter/Common-SourceApproximate Analysis Amplifier with Complementary232 Load 2793 .5 .6 .4 Offset Voltage Drift in 4.3 .3 Common-Emitter/Common-Sourcethe Emitter-Coupled Pair Amplifier with Depletion Load234 2824.4	Voltage and Current References 299A.4.1 Matching Considerations in CurrentMirrors 327A.4.1.1 Bipolar 327A.4.1.2 MOS 329A.4.2 Input Offset Voltage ofDifferential Pair withActive Load 332A.4.2.1 Bipolar 332A.4.2.2 MOS 334CHAPTER 5Output Stages 3445.1 Introduction 344Contents xiii4.3.4 Common-Emitter/Common-Source 5 .2 The Emitter Follower As an OutputAmplifier with Diode-Connected Stage 344Load 2844.3 .5 Differential Pair with 5.2.1 Transfer Characteristics of theCurrent-Mirror Load 287 Emitter-Follower 3444.3.5 .1 Large-Signal Analysis 5.2.2 Power Output and Efficiency 347287 5.2.3 Emitter-Follower Drive4.3.5.2 Small-Signal Analysis Requirements 354288 5.2.4 Small-Signal Properties of the4.3.5.3 Common-Mode Rejection Emitter Follower 355Ratio 2935.3 The Source Follower As an OutputStage 3564.4 .1 Low-Current Biasing 299 5 .3 .1 Transfer Characteristics of the4.4.1 .1 Bipolar Widlar Current Source Follower 356Source 299 5.3.2 Distortion in the Source Follower4.4.1.2 MOS Widlar Current 358Source 3024.4.1 .3 Bipolar Peaking Current 5 .4 Class B Push-Pull Output Stage 362Source 3034.4.1.4 MOS Peaking Current 5.4.1 Transfer Characteristic of theSource 304 Class B Stage 3635.4.2 Power Output and Efficiency of the4.4.2 Supply-Insensitive Biasing 306 Class B Stage 3654.4.2 .1 Widlar Current Sources 5.4.3 Practical Realizations of Class B306 Complementary Output Stages4.4.2 .2 Current Sources Using 369Other Voltage Standards 5.4.4 All-npn Class B Output Stage307 3764.4.2 .3 Self Biasing 309 5.4 .5 Quasi-Complementary Output4.4 .3 Temperature-Insensitive Biasing Stages 379317 5.4.6 Overload Protection 3804.4 .3 .1 Band-Gap-ReferencedBias Circuits in Bipolar 5.5 CMOS Class AB Output Stages 382Technology 317 5.5 .1 Common-Drain Configuration4.4.3.2 Band-Gap-Referenced 383Bias Circuits in CMOS 5.5 .2 Common-Source ConfigurationTechnology 323 with Error Amplifiers 3845.5.3 Alternative Configurations 3915.5.3 .1 Combined Common-DrainCommon-SourceConfiguration 3915.5.3 .2 Combined Common-DrainCommon-SourceConfiguration with HighSwing 3935.5.3 .3 Parallel Common-SourceConfiguration 394CHAPTER 6Operational Amplifiers withSingle-Ended Outputs 4046.1 Applications of Operational Amplifiers405xiv Contents6.1 .1	Basic Feedback Concepts 405 6.6 MOS Folded-Cascode OperationalAmplifiers 4466.1 .2 Inverting Amplifier 4066.7 MOS Active-Cascode Operational613 Noninvertin 5 Amplifier 408. . Amplifiers 4506.1 .4 Differential Amplifier 408 6.8 Bipolar Operational Amplifiers 4536.1 .5 Nonlinear Analog Operations 409 6.8 .1 The do Analysis of the 7416.1 .6 Integrator, Differentiator 410 Operational Amplifier 4566.1 .7 Internal Amplifiers 411 6.8.2 Small-Signal Analysis of the 7416.1 .7 .1 Switched-Capacitor Operational Amplifier 461Amplifier 411 6.8.3 Input Offset Voltage, Input6.1 .7 .2 Switched-Capacitor Offset Current, andIntegrator 416 Common-Mode Rejection Ratioof the 741 4706.2 Deviations from Ideality in Real Oper-ational Amplifiers 419 6.9 Design Considerations for BipolarMlithi Otil Alifionocperaonampers6.2.1 Input Bias Current 419 4726.2.2 Input Offset Current 420 6.9 .1 Design of Low-Drift Operational6.2.3 Input Offset Voltage 421 Amplifiers 4746.2.4 Common-Mode Input Range 421 6.9.2 Design of Low-Input-Current6.2.5 Common-Mode Rejection Ratio Operational Amplifiers 476(CMRR) 4216.2.6 Power-Supply Rejection Ratio CHAPTER 7(PSRR) 422Frequency Response of Integrated6.2.7 Input Resistance 424 Circuits 4886.2.8 Output Resistance 424 7 .1 Introduction 4886.2.9 Frequency Response 424 7 .2 Single-Stage Amplifiers 4886.2.10 Operational-Amplifier Equivalent 7.2 .1 Single-Stage Voltage AmplifiersCircuit 424and The Miller Effect 4886.3 Basic Two-Stage MOS Operational 7.2.1 .1 The Bipolar DifferentialAmplifiers 425 Amplifier: Differential-6.3.1 Input Resistance, Output Mode Gain 493Resistance, and Open-Circuit 7.2.1 .2 The MOS DifferentialVoltage Gain 426 Amplifier : Differential-Mode Gain 4966.3.2 Output Swing 428 7.2.2 Frequency Response of the6.3.3 Input Offset Voltage 428 Common-Mode Gain for a6.3 .4 Common-Mode Rejection Ratio Differential Amplifier 499431 7.2 .3 Frequency Response of VoltageBuffers 5026.3 .5 Common-Mode Input Range 432 7.2 .3 .1 Frequency Response of the6.3.6 Power-Supply Rejection Ratio Emitter Follower 503(PSRR) 434 7232 Frequency Response of the. . .6 .3 .7 Effect of Overdrive Voltages 439 Source Follower 5096.3.8 Layout Considerations 439 7.2.4 Frequency Response of CurrentBuffers 5116.4 Two-Stage MOS Operational 7.2.4 .1 Common-Base-AmplifierAmplifiers with Cascodes 442 Frequency Response 5146.5 MOS Telescopic-Cascode Operational 7.2.4.2 Common-Gate-AmplifierAmplifiers 444 Frequency Response 5157 .3	Multistage Amplifier FrequencyResponse 5168.6.2 Local Shunt Feedback 591Contents xv8 .7 The Voltage Regulator as a Feedback7.3 .1 Dominant-Pole Approximation Circuit 5935167.3 .2 Zero-Value Time Constant 8.8 Feedback Circuit Analysis UsingAnalysis 517 Return Ratio 5997.3 .3 Cascode Voltage-Amplifier 8 .8 .1 Closed-Loop Gain Using ReturnFrequency Response 522 Ratio 6017.3 .4 Cascode Frequency Response 8 .8.2 Closed-Loop Impedance Formula525 Using Return Ratio 6077.3 .5 Frequency Response of a Current 8.8 .3 Summary-Return-Ratio AnalysisMirror Loading a Differential Pair 612532 8.9 Modeling Input and Output Ports in7.3.6 Short-Circuit Time Constants 533 Feedback Circuits 6137.4 Analysis of the Frequency Response ofthe 741 Op Amp 537CHAPTER 97.4.1 High-Frequency Equivalent Circuit Frequency Response and Stability ofof the 741 537 Feedback Amplifiers 6247.4.2 Calculation of the -3-dBFrequency of the 741 538 9 .1 Introduction 6247.4 .3 Nondominant Poles of the 741 9.2 Relation Between Gain and540 Bandwidth in Feedback Amplifiers7.5 Relation Between Frequency 624Response and Time Response 542 9.3 Instability and the Nyquist Criterion626CHAPTER 8 9.4 Compensation 633Feedback 5538.1 Ideal Feedback Equation 5539.4.1 Theory of Compensation 6339.4.2 Methods of Compensation 6378.2 Gain Sensitivity 555 9.4.3 Two-Stage MOS Amplifier8.3 Effect of Negative Feedback on Compensation 644Distortion 555 9.4.4 Compensation of Single-Stage8.4 Feedback Configurations 557 CMOS OP Amps 6528.4.1 Series-Shunt Feedback 557 9.4.5 Nested Miller Compensation 6568.4.2 Shunt-Shunt Feedback 560 9.5 Root-Locus Techniques 6648.4.3 Shunt-Series Feedback 561 9.5 .1 Root Locus for a Three-Pole8.4.4 Series-Series Feedback 562 Transfer Function 6648.5 Practical Configurations and the Effect9.5.2 Rules for Root-Locus Construction667of Loading 563 9.5 .3 Root Locus for Dominant-Pole8.5.1 Shunt-Shunt Feedback 563 Compensation 6758.5.2 Series-Series Feedback 569 9.5.4 Root Locus for Feedback-Zero8.5 .3 Series-Shunt Feedback 579Compensation 6768.5.4 Shunt-Series Feedback 5839.6 Slew Rate 6808.5 .5 Summary 587 9.6 .1 Origin of Slew-Rate Limitations6808.6 Single-Stage Feedback 587 9.6.2 Methods of Improving Slew-Rate8.6.1 Local Series Feedback 587 684xvi Contents9.6.3	Improving Slew-Rate in Bipolar 11 .2.1 Shot Noise 748Op Amps 6859.6.4 Improving Slew-Rate in MOS Op 11 .2.2 Thermal Noise 752Amps 686 11 .2 .3 Flicker Noise (11f Noise) 7539.6 .5 Effect of Slew-Rate Limitations on 11 .2 .4 Burst Noise (Popcorn Noise) 754Large-Signal SinusoidalPerformance 690 11 .2 .5 Avalanche Noise 755A.9.1 Analysis in Terms of Return-Ratio 11 .3 Noise Models of Integrated-CircuitParameters 691 Components 756A.9.2 Roots of a Quadratic Equation 692 11.3 .1 Junction Diode 75611.3 .2 Bipolar Transistor 75711.3 .3 MOS Transistor 758CHAPTER 10Nonlinear Analog Circuits 702 11.3.4 Resistors 75910.1 Introduction 702 11.3.5 Capacitors and Inductors 75910.2 Precision Rectification 702 11 .4 Circuit Noise Calculations 76010.3 Analog Multipliers Employing the 11 .4.1 Bipolar Transistor NoiseBipolar Transistor 708 Performance 76211 .4.2 Equivalent Input Noise and the10.3 .1 The Emitter-Coupled Pair as a Minimum Detectable Signal 766Simple Multiplier 708 11 .5 Equivalent Input Noise Generators10.3.2 The do Analysis of the Gilbert 768Multiplier Cell 71011 .5 .1 Bipolar Transistor Noise10.3 .3 The Gilbert Cell as an Analog Generators 768Multiplier 712 11 .5.2 MOS Transistor Noise Generators10.3 .4 A Complete Analog Multiplier 77371511 .6 Effect of Feedback on Noise10.3 .5 The Gilbert Multiplier Cell as aPerformance 776Balanced Modulator and PhaseDectector 716 11.6 .1 Effect of Ideal Feedback on Noise10.4 Phase-Locked Loops (PLL) 720 Performance 77611.6 .2 Effect of Practical Feedback on10.4.1 Phase-Locked Loop Concepts Noise Performance 77672010.4.2 The Phase-Locked Loop in the11.7 Noise Performance of Other TransistorLocked Condition 722 Configurations 78310.4.3 Integrated-Circuit Phase-Locked 11.7 .1 Common-Base Stage NoiseLoops 731 Performance 78310.4 .4 Analysis of the 560B Monolithic 11.7 .2 Emitter-Follower NoisePhase-Locked Loop 735 Performance 78411.7.3 Differential-Pair Noise10.5 Nonlinear Function Symbols 743 Performance 78511 .8 Noise in Operational Amplifiers 788CHAPTER 11 11 .9 Noise Bandwidth 794Noise in Integrated Circuits 748 11 .10 Noise Figure and Noise Temperature11 .1 Introduction 748 79911 .2 Sources of Noise 748 11 .10 .1 Noise Figure 79911 .10.2 Noise Temperature 802Contents xviiCHAPTER 12	12.5.3 CMFB Using Transistors in theFully Differential Operational Amplifiers Triode Region 830808 12.5 .4 Switched-Capacitor CMFB 83212.1 Introduction 808 12.6 Fully Differential Op Amps 83512.2 Properties of Fully Differential 12.6.1 A Fully Differential Two-Stage OpAmplifiers 808 Amp 83512.3 Small-Signal Models for Balanced 12.6.2 Fully Differential TelescopicDifferential Amplifiers 811 Cascode Op Amp 84512.4 Common-Mode Feedback12.6 .3 Fully Differential Folded-Cascode816 Op Amp 84612.4 .1 Common-Mode Feedback at Low 12.6.4 A Differential Op Amp with TwoFrequencies 817 Differential Input Stages 84712.4.2 Stability and Compensation 12.6.5 Neutralization 849Considerations in a CMFB Loop822 12.7 Unbalanced Fully Differential Circuits12.5 CMFB Circuits 823 85012.5 .1 CMFB Using Resistive Divider 12.8 Bandwidth of the CMFB Loop 856and Amplifier 82412.5 .2 CMFB Using Two Differential Index 865Pairs 828

Analysis and design of analog integrated circuits

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