Böhm, J

Cindro, V

Eklund, L

Gadomski, S

Grillo, A A

Grosse-Knetter, J

Górnicki, E

Koperny, S

Kramberger, G

MacPherson, A L

Malecki, P

Mandic, I

Mikuz, M

Morrissey, M

Pernegger, H

Philips, P W

Polak, I

Smith, N A

Spencer, E

Stastny, J

Turala, Michal

Weidberg, A R

CERN Document Server

Power Supply and Power Distribution System for the ATLAS Silicon Strip DetectorsJ.BohmA , V.CindroD , L.EklundE , S.GadomskiC&E , E.GornickiC , A.A.GrilloI , J.Grosse−KnetterE ,S.KopernyB , G.KrambergerD , A.MacphersonE , P.MaleckiC , I.MandicD , M.MikuzD , M.MorrisseyH ,H.PerneggerE , P.W.PhilipsH , I.PolakA , N.A.SmithF , E.SpencerI , J.StastnyA , M.TuralaC , A.WeidbergG ATLAS SCT CollaborationA Academy of Sciences of the Czech Republic, Prague, Czech RepublicB Faculty of Physics and Nuclear Techniques of the UMM, Cracow, PolandC Institute of Nuclear Physics, Cracow, PolandD Josef Stefan Institute and Department of Physics, University of Ljubljana, Ljubljana, SloveniaE CERN, Geneva, SwitzerlandF Department of Physics, Oliver Lodge Laboratory, University of Liverpool, Liverpool, UKG Department of Physics, Oxford University, Oxford, UKH Rutherford Appleton Laboratory, Chilton, Didcot, UKI Institute of Particle Physics, University of California, Santa Cruz, CA, USAPiotr.Malecki@ifj.edu.plAbstractThe Semi−Conductor Tracker of the ATLAS experimenthas modular structure. The granularity of its power supplysystem follows the granularity of the detector. This systemof 4088 multi−voltage channels providing power and controlsignals for the readout electronics as well as bias voltage forsilicon detectors is described.  Problems and constraints concerning power distributionlines are also presented. In particular, optimal choicebetween concurrent requirements on material, maximumvoltage drop, space available for services, assemblysequence etc.  is discussed.  I. POWER SUPPLY SYSTEM FOR THE ATLAS SCTThe ATLAS SCT detector[1] consists of 4088 modules ofwhich 2112 form four barrel cylinder layers and 1976 aremounted on end cap wheels. Single−sided micro−stripdetectors are glued back−to−back to form one double−sidedmodule with 1536 strips. The module is equipped with ahybrids, a small boards carrying 12 ABCD3T readout chipsand electronics to transfer digital data from and to SCTmodules. Present barrel and end cap hybrids aresubstantially different in many aspects but identical from thepoint of view of power supplies.  A. Basic design principlesThe ATLAS SCT readout chips and electronics for theoptical transmission of digital data to the off−detectorstations (as well as timing, trigger and control data to SCTmodules) require several low voltage supplies. In additionsilicon micro−strip detectors operating in the LHC highradiation environment require the bias voltage which can beregulated in 0 − 500 V range.SCT power supply and power distribution system hasbeen designed according to following basic requirements: modularity of the power supply system follows themodularity of the detector, power supply modules are fully isolated and voltages inmodules are "floating", every detector module is powered by separate, multiwireline (tape or cable).In the context of this article it seems appropriate tounderline that among other consequences for the detectorperformance the above mentioned design rules allow forthe maximum flexibility in selection of optimal shieldingand grounding schemeB. Requirements for Low Voltage powersuppliesPresent requirements[2] for low voltage power suppliesresult from several iterations of readout chip design andfrom many beam and radiation tests of moduleprototypes. Main objects of concern are Vcc, "analog"voltage supplying analog circuits of the readout chip,and Vdd, "digital" voltage supplying digital part of theABCD3T chip, as well as electronics for the opticallinks (DORIC4 and VDC ASICs). These two voltagesshould provide relatively high currents of the order of1A. Their load may, in addition, vary over a widerange.Low voltage power supply channel should also provideseveral low power voltages and control signals: biasvoltage for the photodiode, control voltage for VDCASIC, voltage (two current sources) for the temperaturemonitoring, module reset and clock select signals.Nominal values for voltages and signal levels withtypical and maximal loads are listed in Table 1. Theinclusion of these extra power and control signals, aswell as the temperature readout mentioned in section Gbelow, in the low voltage supply channel is to insure acommon reference potential for all electrical signals onthe detector module. This minimises the possibility forelectrical pick−up or extraneous noise.  Table 1: LV Power RequirementsName Nominalvalue [V]Current[mA]Max.Current[mA]Vcc 3.5 900 1300Vdd 4.0 570 1300VCSEL 1.6 − 6.6 6 8PIN bias 10.0 0.5 1.1Currentsource 0Max.  8.0 0.08CurrentSource 1Max.  8.0 0.08RESET Vdd/−0.7 0.4SELECT Vdd/−0.7 1.3These main requirements, together with others referringto voltage setting resolutions, voltage and currentmonitoring accuracy, over voltage and over current triplimits and maximum output ripple, lead to specificationsfor LV power supplies which have recently been fixed[2].C. HV requirementsBias voltage power supplies should provide stable,digitally controlled voltage in 0 − 500 V range andprecise measurement of the output current in 40 nA −5mA range. One should be able to set the current triplimit individually for each channel in range fromhundreds nA to 5 mA as well as select one of thepredefined voltage ramping rates: 50, 20, 10, 5 V/s. It isalso required that the maximum allowable noise level isnot higher than 40 mV peak to peak[3].  D. Basic block characteristicsSeveral low voltage modules are grouped onto one boardequipped with the board micro−controller. The lowmulti−voltage power module[4] consists of separatefloating supplies for analog and digital voltages. Eachmodule is controlled and monitored by its own micro−controller which receives commands and receives ortransmits data to/from the board micro−controller.  The HV power module has very similar structure andsimilar basic components: rectifier, filter, regulator,error amplifier, DAC and ADC.  Two voltages of a relatively high current, Vcc and Vdd,differ from others by using sense wires. This isnecessary for the considerable resistance of eachtransmission line and hence the considerable voltagevariation at the module side in response to variations ofthe current draw. Analog data from sense wires isconverted to digital and processed by the channelmicro−controller for the appropriate output voltageadjustment.  LV and HV channels are powered from the 48V, 48 kHzsquare wave generators. An isolation of individualchannels and individual voltages is realised by HFtransformers on the power path and by optical couplerson communication lines.More details concerning design and performance ofprototypes of the LV power supply modules are in ref.[4]. HV power supply module design has beenpresented in the Proceedings of the previous, 6−thWorkshop on Electronics for the LHC Experiments [5].E. LV/HV integrationLow and high voltage power supplies form together onesystem. Multi−channel LV and HV 6U cards areintegrated in common 19’’ EURO crate equipped withthe custom back plane, the crate controller, the interlockcard, and a common power pack. One crate will house48 SCT power supply multi−voltage channels mountedon 12 LV cards, 4 channels each, and on 6 HV cards,each containing 8 channels.  All cards in one crate are supplied from the crate 1.6 kWpower pack which provides 48V, 48 kHz square wavefor HF transformers and DC supply for the commercialcrate controller as well as for all card controllers.All SCT LV power supply cards are identical.Similarly, there is full interchangeability between HVpower supply cards. The card address and consequentlythe channel address is determined from the card positionin the crate. The custom back plane design predefinespositions for LV and HV cards. The mechanicalconstruction prevents card misplacement.It has been decided to use commercial crate controllerwhich communicates within the crate with the eighteencard controllers via parallel 8−bit bus. Thiscommunication is serviced by a simple and efficientcustom made protocol.  The crate controller is equipped with the CAN businterface for communication with the higher levels ofthe Detector Control System.Custom back plane bears on the back side special 48connectors for the multi−wire cables which connectpower supply modules with the first patch panel (PP3)on the way to detector modules. These connectors(CONEC 17W5) have five thick pins allowing forconnection of four high cross section wires and anotherwire with hv insulation. Twelve thin pins serve the restof low current lines (of which one is reserved for thedrain wire of the cable).  F. Location of power suppliesThe choice of the power supplies location has importantimplications on the power distribution system, discussed inthe next section, as well as on the power supply design andspecifications. For example, the maximum power pathlength determines the maximum voltage drop and hence themaximum output voltage which power supply must provideto reach the nominal value at the detector side. Anticipatingsome results of the following discussion it is worth tomention here that the Vcc supply should be designed for themaximum output voltage of 8.75 V and Vdd for 9.33 V to beable to provide the nominal values on the detector moduleside in the case of the maximum voltage drop (with 1 Vmargin included)[2].  The standard location for the off−detector electronics isin the cavern (named USA15) next to the detector hall. Forsuch location the length of the power path will be in range of100 − 130 m. SCT plans to locate 50% of its power supplycrates in another cavern, on the other side of ATLASdetector (named US15). This will shorten the path length by30 − 40 m for that part of modules, making the longest pathabout 100m. II. POWER DISTRIBUTION FOR THE ATLAS SCTAbout 23 kW are needed for the normal operation of theATLAS SCT. The delivery of that power to the inner part ofthe Inner Detector can not be done without extra material,more power dissipation, space for services, cost etc. In thefollowing short review we will concentrate on a group ofrequirements which mostly concern high current lines forVcc and Vdd voltages. Grounding and shielding problems,which are very important for the system of thousands ofwires distributed over large surfaces, are discussed elsewhere[6].G. List of linesIn the following list the first four lines, out of allseventeen, should have considerably larger cross section toconduct high current, 1.3 A maximum. All other lines canpractically use as thin conductor as technologically possible.1. Vdd − digital voltage 2. DGND − digital ground3. Vcc − analog voltage4. AGND − analog ground5. HV − bias voltage 6. Hvgnd − bias ground7. Vddsense8. DGNDsense9. Vccsense10. AGNDsense11. VCSEL − driver12. SELECT − clock redundancy13. RESET − clock14. PIN − diode bias15. TEMP1 − sensor16. TEMP2 − sensor17. drain wireSeveral voltages (VCSEL, SELECT, RESET,PIN.TEMP1, TEMP2) use the digital ground, DGND, as thecommon return. In all present tests of SCT moduleprototypes analog and digital grounds are directly connected.AGNDsense and DGNDsense wires sense then the samepoint but it has been agreed to keep both lines as the presentlaboratory practice may not be continued in the finalinstallation.  H. Conflicting requirementsThe design of the power delivery system for the detectorlocated in the innermost part of the ATLAS experimentalsetup should satisfy several conflicting requirements. Oneshould minimise material, voltage drop, power dissipationand costs. One should observe rules concerning the radiationhardness of and flame resistance of materials used. Thedesign is also strongly influenced by the limited space forservices as well as by the foreseen assembly sequence.An optimisation process has different priorities indifferent regions of the detector. Consequently, it has beendecided to divide the power path between the SCT modulesand power supplies into four parts.  I. 4−fold wayFinal design of the power distribution system for theATLAS SCT is in progress and is closely related to theprocess of integration of all services.  1) Low mass tapesIn the innermost part material introduced by cables seemsto be the most critical parameter. This first part, fromdetector modules to the first patch panel (PPB1 for thebarrel, PPF1 for end cap modules) located at the cryostatwall, is served by low mass tapes [7]. These tapes are madefrom 25 micron thick Kapton and 25 micron glue substratewith 50 micron aluminium conductors covered by anotherKapton and glue layer of 25 micron. The width of conductorlines as well as the space between conductors can −fortechnological reasons −be made in steps of 0.5 mm. Ourfour critical lines (for Vcc and Vdd) are chosen to be 4.5 mmwide while all other lines have the minimal allowable widthof 0.5 mm. The length of these tapes is in range 0.7 − 1.6 mfor barrel modules and reaches about 3 m for some of endcap modules. A contribution to the material budget is oftencharacterised by calculating a cumulative amount of materialin certain region of the detector and "dilute" it over somecharacteristic surface. An example for 6 tapes serving onebarrel half stave averaged over the surface of one moduleshows the material contribution of about 0.24% of Xo.  Total maximum power dissipated by low mass tapes isestimated on about 3 kW. Maximum voltage drop for somebarrel tapes reaches 0.6V and for end cap tapes 1 V.2) "Very thin" cablesIt is estimated[8] that the distance from the PPB1 (barrel)to the next patch panel PP2 should not exceed 9 m andthe corresponding one for the end cap (PPF1 − PP2) 5 m.Final numbers depend on the PP2 location and details ofrouting, subject of the decision of the ID coordination.We have originally planed to use Al on Kapton tapes alsofor this part, but with the conductor thickness increasedto 100 micron. As the maximum allowable voltage dropbecome the most critical parameter it has been decided touse the copper conductors.Maximum allowable voltage drop requires specialattention because if it exceeds certain limit then, in caseof a sudden loss of load, the safe limit of 5.5 V for thereadout chip is exceeded.  It is planned to use the multi−wire round cable of 6 mmouter diameter, with a thin Kapton insulation and withthe four high current lines of 0.6 mm2. With such choicethe maximum voltage drop will not exceed 1.6 V for Vccor 1.4 for Vdd what is safe providing that the somevoltage limiters are installed on the PP2. These limitersseem to be unavoidable since another 2V drop has still tobe considered for the rest of the power path.  3) Thin conventional cablesFor the part which extends from patch panels PP2 andPP3 of length of about 20 m it is planned to use multi−wire "conventional" cable[8] with somewhat complicatedgeometry taking into an account the requirement oftwisting wires in groups belonging to the same voltage(e.g. Vcc, AGND, Vccsense and AGNDsense). Withsuch requirement the cable outer diameter is about 12mm with the cross section of our four critical lines equal1 mm2. Maximum voltage drop for that part is estimatedon 1.3 V.4) Thick conventional cablesThe distance from PP3 to power supply crates depends onthe final location of PS racks. ATLAS SCT considersuse of two locations in caverns on both sides of thedetector hall. That will considerably shorten the path forthick conventional cables, and hence reduce powerdissipation, cost etc. The multi−wire cable[8] with thegeometry similar to the thin conventional cable will havethe four critical lines with the 4 mm2cross section andthe outer diameter of about 20 mm. The estimatedmaximum voltage drop equals about   1V.J. Final remarksThe power distribution system for the ATLAS SCT is inthe development state. Several elements require finaldesign and tests.  In particular: final construction and location of patch panels aswell as final details of routing of cables. Thisdepends strongly on the overall process ofintegration with other subsystem and involvessome coordination on the level of the InnerDetector full power dissipation by cables in all fourregions is estimated on 10 kW (for nominalcurrents and maximal cable lengths)[8]. Tosatisfy the "rule of thermal neutrality" of eachsubdetector one has to find solution for the cablecooling in some regions total voltage drop along power linesconsiderably exceeds the safety limit for thereadout ASICs and some voltage limiters have tobe installed in the region of PP2. An appropriatevoltage limiter circuit has been designed for PP2and is now undergoing system and radiationtesting PP3 is being designed with common−modeinductors to filter unwanted pick−up from thelong cable runs from the power supplies.Prototypes have been tested in the system testand have been shown to be quite beneficial.  III. REFERENCES1. ATLAS Inner Detector TDR Volume 2CERN/LHCC/97−17 p 3852. J.Bohm, SCT Week Prague 25 − 29 June 2001http://atlas.web.cern.ch/Atlas/GROUPS/INNER_DETECTOR/SCT/sct_meetings.html3. http://www.ifj.edu.pl/ATLAS/sct/scthv/4. http://www−hep.fzu.cz/Atlas/WorkingGroups/Projects/MSGC.html 5. P.Malecki. Multichannel System of FullyIsolated HV Power Supplies or Silicon StripDetectors, 6−th Workshop on Electronics forLHC Experiments. CERN/LHCC/2000−041.p.376 6. Ned Spencer. ATLAS SCT/Pixel Groundingand Shielding Note. Nov 22. 1999. UCSC.EDMS Id:108383, Number ATL−IC−EN−0004v.17. http://merlot.ijs.si/~cindro/low_mass.htmlhttp://www−f9.ijs.si/atlas/8. H.Pernegger.Services in:http://perneg.home.cern.ch/perneg/ 

Power Supply and Power Distribution System for the ATLAS Silicon Strip Detectors

Power Supply and Power Distribution System for the ATLAS Silicon Strip Detectors

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