Bocci, V

Chiodi, G

Di Marco, S

Gennari, E

Petrolo, E

Salamon, A

Vari, R

Veneziano, Stefano

CERN Document Server

Prototype Slice of the Level-1 Muon Trigger in the Barrel Region of theATLAS ExperimentV.Bocci, G.Chiodi, S.Di Marco, E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.VenezianoINFN Sezione di Roma, P.le Aldo Moro 2, 00185 Rome, ItalyRiccardo.Vari@roma1.infn.itAbstractThe ATLAS barrel level-1 muon trigger system makes useof the Resistive Plate Chamber detectors mounted in threeconcentric stations. Signals coming from the first two RPCstations are sent to dedicated on detector ASICs in the low-pTPAD boards, that select muon candidates compatible with aprogrammable pT cut of around 6 GeV, and produce an outputpattern containing the low-pT trigger results. This informationis transferred to the corresponding high-pT PAD boards, thatcollect the overall result for low-pT and perform the high-pTalgorithm using the outer RPC station, selecting candidatesabove a threshold around 20 GeV. The combined informationis sent via optical fibre to the off-detector optical receiverboards and then to the Sector Logic boards, that count themuon candidates in a region of ∆η×∆φ=1.0×0.1, and encodethe trigger results. The elaborated trigger data is sent to theCentral Trigger Processor Muon Interface on dedicatedcopper link. The read-out data for events accepted by thelevel-1 trigger are stored on-detector and then sent to the off-detector Read-Out Drivers via the same receiver boards usedfor trigger data, sharing the bandwidth.A trigger slice is made of the following components: asplitter, a low-pT PAD board, containing four CoincidenceMatrix boards; a high-pT PAD board, containing 4 CM boardsand the optical link transmitter; an optical link receiver; aSector Logic board; a Read-Out Driver board.I. THE ATLAS BARREL LEVEL-1 MUON TRIGGERThe ATLAS muon spectrometer in the barrel, whichcovers a pseudorapidity region equal to |η| < 1.05, makes useof the Multi Drift Tube detectors for particle track precisemeasurement, and the Resistive Plate Chamber detectors fortriggering.The barrel first level muon trigger has to process the fullgranularity data (about 350.000 channels) of the triggerchambers [1]. The latency time is fixed and less then 2.5 µs.The maximum data output frequency to the higher-leveltriggers is 100 kHz.A. Trigger AlgorithmLevel-1 trigger main functions are:− identification of the bunch crossing corresponding tothe event of interest;− discrimination of the muon transverse momentum pT;− fast and coarse muon tracking, used for higher-leveltrigger processors;− second coordinate measurement in the non-bendingprojection with a resolution of ~1 cm.The level-1 trigger is able to operate with two differenttransverse momentum selections, providing a low-pt trigger(pT ~ 5.5 GeV), and a high-pT trigger (pT ~ 20 GeV). Toreduce the rate of accidental triggers, due to the low energybackground particles in the ATLAS cavern, the algorithm isperformed in both η and φ, for both low-pT and high-pTtriggers. Barrel precision MDT chambers can only measurethe bending coordinate, thus the φ projection is used to give tothe experiment the non-bending muon coordinate with aresolution of ~1 cm. The measured non-bending coordinate isused in addition with the data coming from MDT detectors forprecise particle track reconstruction.A section view of the trigger system is represented inFigure 1, showing where the three RPC stations are locatedinside the ATLAS Muon Spectrometer. The ATLAS muontrigger system is composed by three RPC stations. The RPCdetectors are mounted on the MDT chambers.Figure 1: The ATLAS Muon Spectrometer LayoutEach RPC chamber is readout by two planes of orthogonalstrips. The η strips give the bending projection, while the φstrips give the non-bending one.Muon pT selection is performed by a fast coincidencebetween strips of different RPC planes. The number of planesin the whole trigger system has been chosen in order tominimise accidental coincidences and to optimise efficiency.For accidental counting reduction, the trigger operates in bothbending and non-bending projection.Figure 2 shows the trigger scheme. The low-pT algorithmmakes use of information generated from the two BarrelMiddle stations RPC1 and RPC2. The first stage of thealgorithm is performed separately and independently in thetwo η and φ projections. If a track hit is generated in theRPC2 doublet (pivot plane), a search for the same track ismade in the RPC1 doublet, within a window whose centre isdefined by an infinite momentum track coming from theinteraction point. The width of the window is programmableand selects the desired cut on pT (the smaller the window, thehigher the cut on pT). Three programmable pT thresholds ineach projection can be applied simultaneously. To cope withthe background from low energy particles in the cavern, amajority coincidence of the four hits of the two doublets ineach projection is required.The high-pT algorithm makes use of the result of the low-pT trigger system and the hits available in the RPC3 station. Acoincidence between the 1/2 majority of the RPC3 doubletand the low-pT trigger pattern is required.Figure 2: The ATLAS Barrel Level-1 Muon TriggerB. Trigger SegmentationThe ATLAS barrel trigger system is composed of twoindependent trigger subsystems, the first in the region ofpositive η values, called barrel system 0, the second, thebarrel system 1, in the negative η region [2]. Each barrelsubsystem (6.7 m < r < 10.5 m) is made of 8 Large Sectors, 6Small Sectors, and 2 Special Chambers Sectors in the feetregion. Each Sector is organized in three Trigger Stations,RPC1 and RPC2 placed on the external sides of the BarrelMiddle MDT chambers, and the RPC3 in the innermost oroutermost side of the Small or Large Outer MDT chambers.RPC stations dimension has been chosen to match thedimension of the corresponding MDT chamber. On each half-barrel plane (positive or negative η) there are 6 or 7 RPCmodules along z, depending if the sector is respectively largeor small. Each RPC module is composed by two RPCchambers, partially overlapping in the η direction (see Figure3), and is read in two equal independent φ sub-sectors, calledTrigger Sectors. Each trigger sector is segmented in PADsand Regions Of Interest.Figure 3: Schematic view of an RPC moduleEach PAD covers a region of ∆η×∆φ ~ 0.2×0.2. Inside aPAD the trigger is segmented into RoIs, each one covering aregion given by the overlap of one η and one φ CoincidenceMatrix. The Coincidence Matrix is responsible for collectingsignals from RPC η and φ strips, and performing thecoincidence and majority logic. The dimension of aCoincidence Matrix is either ∆η×∆φ ~ 0.2×0.1 for the ηCMAs, or ∆η×∆φ ~ 0.1×0.2 for the φ CMAs, the dimension ofone RoI is ∆η×∆φ ~ 0.1×0.1.The total number of PADs in the barrel is 832, the totalnumber of RoIs is 1664.Figure 4: ATLAS Barrel Half SectorII. HARDWARE IMPLEMENTATIONThe trigger slice scheme is shown in Figure 5. Signalscoming from the RPC detectors are amplified, discriminatedand digitally shaped on-detector. The Amplifier DiscriminatorShaper boards, each one containing eight channels, aremounted on the four sides of each chamber module, on oneend of the RPC strips.The level-1 trigger algorithm and data transmissionelectronics is contained in PAD Boxes mounted on the RPCs.Signals coming from the front-end electronics have to be sentvia copper cables to the Coincidence Matrix ASICs (CMA),which have to perform the trigger algorithm [3]. Because ofoverlapping coincidence windows, a single RPC channel candrive more then one CMA input. For this reason, signalscoming from RPC1 and RPC3 stations are sent to dedicatedSplitter Boards that can fan-out incoming signals and send theoutput to the appropriate CMAs. Signals coming from thepivot plane RPC2 are directly connected to the CMAs.RPC1 and RPC2 signals are sent to the low-pT CMAs,while RPC3 signals and the output from the low-pT trigger aresent to the high-pT CMAs.Figure 5: ATLAS Level-1 Barrel Muon Trigger SliceFour low-pT CMAs, covering a total region of ∆η×∆φ ~0.2×0.2, are mounted on a low-pT PAD board, the four high-pT CMAs are mounted on a high-pT PAD board. The low-pTPAD board collects data coming from the four low-pT CMAs,and sends trigger data to the high-pT PAD board, whichcollects low-pT and high-pT data and serially sends data off-detector via an optical fibre. The optical receiver, located inthe counting room, receives serial data from the optical fibre,and sends them to the Sector Logic board and to the Read-OutDriver.The on-detector electronics will be mounted on top on theRPC detectors as shown in Figure 6. A Splitter Box containstwo or three splitter boards, depending on the required fan-out. In order to reduce the number of interconnections, eachcouple of φ strips in one RPC detector belonging to twoadjacent RPC chambers is wire or-ed on detector.Figure 6: Schematic view of a Barrel Middle RPC stationA. Coincidence Matrix ASICThe CMA is the core of the level-1 trigger logic, its mainfunctions are:− incoming signal timing alignment;− input and output signal masking;− de-clustering algorithm execution;− majority logic;− trigger algorithm execution;− level-1 latency memory data storing;− readout data formatting, storing and serialtransmitting.A schematic view of the chip internal architecture and itsmain block division is represented in Figure 7.The CMA can be programmed to perform either the low-pT or the high-pT trigger algorithm. The chip can be used as aη CMA, covering a region ∆η×∆φ ~ 0.2×0.1, or as a φ CMA,covering a region of ∆η×∆φ ~ 0.1×0.2.The chip has 2×32 + 2×64 inputs for the front-end signals[4]. In the low-pT CMAs the 2×32 inputs are connected to thefront-end signals, either η strips or φ strips, coming from adoublet of the RPC2 pivot plane, while the 2×64 inputs areconnected to the signals coming from the RPC1 doublet. Forthe high-pT CMAs the first 32 inputs are connected to theoutput trigger signals coming from the low-pT PAD board, thesecond 32 inputs are not used, while the 2×64 inputs areconnected to the signals coming from the RPC3 doublet.The CMA aligns in time the input signals in step of one-eight of a bunch crossing period. For this reason the chipinternal working frequency is 320 MHz, eight times the 40MHz bunch crossing frequency. Input signals can be maskedto the zero logic in order to be able to suppress noisy channelsand to handle unconnected input signals.RPC average cluster size is ~1.4, hence input signals arepre-processed and de-clustered in order to sharpen the pT cut.The maximum cluster size to be processed in the de-clusteringlogic is programmable.Processed input signals are sent to the coincidence logic,which performs the coincidence algorithm. The logic isrepeated three times, so that three different coincidencewindows can be simultaneously applied inside the chip. Thethree coincidence windows can be independentlyprogrammed, thus providing three different muon pT cuts.Coincidence logic inputs can be masked to “one” logic, tosimulate unconnected inputs. A programmable majority logiccan be applied to the coincidence algorithm, choosing a 1/4,2/4, 3/4 or 4/4 plane confirmation. The 32-bit trigger outputpattern is then sent to the chip outputs.Figure 7: CMA block schemeThe CMA readout logic collects chip input data andtrigger output data in a latency memory, used to store eventsduring level-1 latency period [5]. Data corresponding to oneevent are accepted according to the Level-1 Accept signalarrival time and to the programmed acceptance window time.All other hits are discarded, while level-1 validated data areformatted and sent to de-randomising buffers for the serialreadout.The CMA chip has ~ 300 internal registers programmablevia I2C bus. Single Event Upset detection logic has beenimplemented for all registers, redundancy logic has beenimplemented for critical control registers.CMA design has been realized with a 0.18 µm CMOStechnology. The external clock frequency is 40 MHz, theinternal working frequency is 40 MHz for registerinitialisation, 320 MHz for the pipeline and trigger logic, 160MHz for the readout logic. An internal PLL has been used forclock frequency multiplication. JTAG boundary and scanchain logic has been implemented for test purposes. TheCMA has ~ 500.000 basic cells, including ~ 80 kbit ofinternal memory. Chip area is ~ 20 mm2, power dissipation is< 1 W.B. PAD Logic boxesThe first step of the trigger algorithm is performedseparately in the η and in the φ projections. Four CM boards,each one mounting one CMA, are plugged on one PAD board,which is responsible to collect data coming from two η CMAsand two φ CMAs, to elaborate incoming data and to associatemuon candidates in the Region-Of-Interest ∆η×∆φ ~ 0.1×0.1.Globally the PAD logic board covers a region ∆η×∆φ ~0.2×0.2. A dedicated FPGA chip performs the PAD logic. Itcombines η and φ information, selects the higher triggeredtrack in one RoI and solves overlaps inside the PAD.Timing, trigger and control signals are distributed in thePAD boards from the TTCrx ASIC, which will be mounted ona dedicated plug-in board.In the low-pT PAD board, which is mounted on the RPC2detector, low-pT trigger result and the associated RoIinformation is transferred, synchronously at 40 MHz, to thecorresponding high-pT PAD board via copper cables, usingLVDS signals. LVDS driver and receiver chips are mountedon the PAD board. The high-pT PAD board, which is mountedon the RPC3 detector, is similar to the low-pT one. It performsthe high-pT algorithm, collects the overall result for both thelow-pT and the high-pT trigger and sends the readout data tothe Read Out Driver via optical link. The custom built opticallink is mounted on a dedicated board to be plugged on thehigh-pT PAD board.The Embedded Local Monitor Board, a general-purposeCANBUS plug-in board (CERN & Nikhef project) is used inboth the PAD boards for JTAG and I2C chip initialisation andfor local control and monitoring.Each PAD board is enclosed in a liquid cooled PAD Boxthat will be mounted on the RPC detector.C. Off-detector electronicsThe optical link board in the high-pT PAD box transmitsthe trigger and readout data to the receiver board located inthe USA 15 counting room. One Receiver board receives theinputs from four optical links and sends the output to theSector Logic board and to the Read Out Driver board.Proposed crate for containing Receiver boards, RODboards and Sector Logic boards is 6U VME 64X format. Asingle crate contains 8 Receiver boards, 4 Sector Logicboards, 2 ROD boards and a ROD controller, as shown inFigure 8.The Sector Logic covers a region ∆η×∆φ = 1.0×0.2, eachSL board receives data from 7 high-pT PAD logic boards inthe small sectors and 6 high-pT PAD logic boards in the largesectors [6]. It maps the signals coming from the TileCalorimeter trigger towers to the triggered muons, it performsouter plane confirmation for all the three low-pT thresholds, itsolves the η overlap inside the sector, it selects the two higherthresholds triggered in the sector, associating with each muona region of interest ∆η×∆φ ~ 1.0×0.1.The outputs from the Sector Logic boards are sent to theMuon Central Trigger Processor Interface via paralleldifferential LVDS links.RODSector logicData/Trigger RXSector logicData/Trigger RXData/Trigger RXData/Trigger RXRODSector logicData/Trigger RXSector logicData/Trigger RXData/Trigger RXData/Trigger RXCPU (DAQ/DCS)LANMUCTPIFE linkRO linkTTC RXROD_BUSYFigure 8: Off-detector crate with the contained VME cardsIII. RADIATION ASSURANCERadiation effects for the level-1 muon trigger electronicshave to be taken into account, since on-detector electronicswill be mounted on the RPC detectors. Radiation levels forthe RPCs have been simulated, Figure 9 and Figure 10 showthe simulated total dose and the > 20 MeV neutrondistribution inside the experiment.Pre-selection and qualification of electronic componentshave to be made following the ATLAS Standard TestMethods [7]. Components have to be qualified for SingleEvent Effects and for Total Ionising Dose.The ATLAS Radiation Tolerance Criteria for TID is:RTCtid = SRLtid · SFsim · SFldr · SFlot · 10y, where the SafetyFactors depend on simulation accuracy, low dose rate effectsand components lot differences. The Simulated RadiationLevels for the RPC are shown in Table 1. The resulting RTCtidis of the order of 1 krad, depending on the electronicscomponent type.For Single Event Upsets the foreseen soft SEU rate is:SEUf = (soft SEUm / ARL) · (SRLsee / 10y) · SFsim, whereSEUm is the number of measured soft SEU during test, andthe Applied Radiation Level is the integrated hadrons fluxreceived by the tested component.SEE and TID pre-selection test have been completed foralmost all the electronics components that will be mounted onthe RPCs. All tested components successfully passed theradiation tolerance criteria. No Single Event Latchup wasobserved, and the foreseen soft SEU frequency for thecomponents that had SEU is low enough for notcompromising trigger functionality. All tested componentsfunctionality was not altered after the maximum foreseen totaldose.A few components have still to be tested. Final componentpre-selection is supposed to be completed during 2002.Figure 9: ATLAS Simulated Total Ionisation DoseFigure 10: ATLAS Simulated Hadrons DistributionTable 1: ATLAS Barrel RPC Radiation LevelsSIMULATED RADIATION LEVELSRLtid[Gy·10y-1]SRLniel[1 MeV n·cm-2·10y-1]SRLsee[> 20 MeV h·cm-2·10y-1]BMF 3.02 2.49·1010 4.69·109BML 3.04 2.82·1010 5.65·109BMS 3.03 2.50·1010 4.73·109BOF 1.19 2.14·1010 4.08·109BOL 1.33 2.20·1010 4.21·109BOS 1.26 2.10·1010 4.10·109IV. CONCLUSIONSAll prototype components produced up to nowsuccessfully passed lab tests. Coincidence Matrix ASIC ismissing to complete the Trigger Slice, and is planned to beavailable by the end of 2001. Further test on RPC chamberson cosmic ray is planned before having the CMA.A C++ high-level simulation code for the level-1electronics is being developed for trigger functionalityconfirmation. CMA VHDL simulation has been comparedwith C++ simulation, giving good crosscheck results.Irradiation test for components pre-selection andqualification are planned to be finished before the end of2002. First slice test will be performed during next year.V. REFERENCES[1] ATLAS Level-1 Trigger TDR[2] E. Gennari, S. Di Marco, A. Nisati, E. Petrolo,A. Salamon, R. Vari, S. VenezianoBarrel Large RPC Chamber Sectors Readout andTrigger Architecture[3] E. Petrolo, A. Salamon, R. Vari, S. VenezianoBarrel LVL1 Muon Trigger Coincidence Matrix ASICUser Requirement Document (ATL-COM-DAQ-2000-050)[4] E. Petrolo, A. Salamon, R. Vari, S. VenezianoCMA ASIC Hardware Requirement document (ATL-COM-DAQ-2001-005)[5] E. Petrolo, A. Salamon, R. Vari, S. VenezianoReadout Requirements in the Level-1 Muon TriggerCoincidence Matrix ASIC (ATL-COM-DAQ-2000-052)[6] V. Bocci, A. Di Mattia, E. Petrolo, A. Salamon, R. Vari,S.VenezianoThe ATLAS LVL1 Muon Barrel Sector Logicdemonstrator simulation and implementation (ATL-COM-DAQ-2000-051)[7] ATLAS Policy in Radiation Tolerant Electronicshttp://atlas.web.cern.ch/Atlas/GROUPS/FRONTEND/radhard.htm

Prototype Slice of the Level-1 Muon Trigger in the Barrel Region of the ATLAS Experiment

Prototype Slice of the Level-1 Muon Trigger in the Barrel Region of the ATLAS Experiment

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