Magazzù, G

Marchioro, A

Moreira, P

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A rad-hard 8-channel 12-bit resolution ADCfor slow control applications in the LHC environmentG. Magazzù 1, A. Marchioro 2, P. Moreira 21 INFN-PISA, Via Livornese 1291 – 56018 S.Piero a Grado (Pisa), Italy (Guido.Magazzu@pi.infn.it)2 CERN, 1211 Geneva 23, SwitzerlandAbstractThe damage induced by radiation in detector sensorsand electronics requires that critical environmentalparameters such as leakage currents of the silicondetectors, local temperatures and supply voltages arecarefully monitored. For the CMS central tracker, anASIC, the Detector Control Unit (DCU) has beendeveloped to monitor these quantities in a commercialsub-micron technology. A set of layout design rulesguarantees for this device the radiation hardness that isrequested for the LHC environment. The key circuit ofthe DCU is an 8-channel 12-bit resolution ADC. Thestructure and the performances of this ADC are describedin this work.I. INTRODUCTIONThe CMS tracker silicon micro-strip detectors, whenexposed to the LHC high levels of radiation, are subjectto a number of damaging phenomena. The main effectsare an increase of the detector leakage current and achange in the detector depletion voltage. Maintaining thedetector integrity and efficiency over their expected 10years life requires careful monitoring of the detectorenvironmental conditions. A VLSI circuit, the DetectorControl Unit (DCU), has been developed for that purposein the CMS tracker.The detector hybrid block diagram is shown in Figure1. The figure represents the global relations between theDCU, the Si micro-strip detectors and the readout chips(the APVs) [1]. The detector leakage currents aremonitored using a sensing resistor. This voltage ismeasured by the DCU Analogue-To-Digital Converter(ADC) and can then be read by the slow control systemusing the DCU I2C interface [2]. The sensor temperatureis measured in two different points using two NegativeTemperature Coefficient (NTC) thermistors in parallel. Athird NTC thermistor is used to monitor the temperaturenear the APV ICs. Two temperature and power supplyindependent currents (20µA and 10µA) are generatedinside the DCU and used to drive the thermistors. TheAPV power supply voltages (2.5V and 1.25V) aremonitored by the DCU through two external resistivedividers.Figure 1: CMS Tracker monitoring systemA single ADC is used inside the DCU to convert theseveral input voltages using an analogue 8-to-1multiplexer.II. DCU DESCRIPTIONThe global architecture of the DCU is shown in Figure2.Figure 2: DCU architectureThe DCU is composed of the following blocks: an 8-to-1 analogue multiplexer, a 12-bit ADC, an I2C interfaceand, a band-gap voltage reference and two temperatureand power supply independent current sources. In thefinal version of the ASIC a diode based integratedtemperature sensor has been added. Due to lack ofexperimental results this last feature will not be describedhere.This work will be focused on the operation andperformance of the analogue multiplexer and the ADC.The design specifications are summarised in Table 1.Table 1: DCU Specifications# of channels 8Resolution 12 bitsInput Range GND→1.25VINL 1 LSBDNL 1 LSBPower Dissipation < 50 mWChip Size < 2mm x 2mmConversion Time < 1 msThe ADC architecture is of a single slope type[3]. In this type of circuits a constant current charges acapacitor. The resulting voltage "ramp" is compared withthe input voltage. A counter is started at the beginning ofthe conversion cycle and measures the time the capacitorvoltage takes to reach the input voltage value. The finalcount is proportional to the input voltage and representsthe conversion result. For the 12-bit ADC described here,the maximum conversion time is 100us (4096 clockcycles at 40MHz).Two ADC operation modes are possible. In onemode the measurement is made with reference to groundwhile in the other mode the power supply (2.5V) is takenas the signal reference. These two modes, allow tomeasure, without loss of linearity, signals that are eitherclose to ground (low input range) or the power supplyvoltage (high input range).When operating in the Low Input Range (LIR)mode the ADC integration capacitor is charged fromground until it reaches the signal voltage, while in theHigh Input Range (HIR) mode the capacitor is dischargedfrom the power supply voltage. Depending on theoperation mode A PMOS (LIR mode) or an NMOS (HIRmode) based comparator is used to take advantage fromtheir intrinsic common mode ranges. Both comparatorsuse a two-stage topology with positive feedback.In order to guarantee high linearity and lowthermal sensitivity the ADC integration capacitor wasimplemented using a metal-to-metal (MIMCAP) 100pFcapacitor. However, the non-linear gate capacitance of theinput transistors of the two comparators is connected inparallel to the integration capacitor degrading the globalnon-linearity of the ADC. To limit the effect of this non-linear component of the total capacitance, the size of theinput transistors has been chosen to be as small aspossible. However, small devices result in largecomparator offsets. To circumvent this problem, thefollowing offset cancellation scheme has beenimplemented: for each data acquisition, two ADCconversions are performed with the capacitor and theinput voltages connected to alternative inputs of thecomparator as shown in Figure 3. The average of thesetwo measurements is taken as the true result of themeasurement. The offset is cancelled because in the twoconsecutive measurements it appears with opposite signs.Figure 3: automatic offset cancellationThe IC interfaces with the tracker control systemthrough an I2C bus. This is used to start the acquisitions,to select the input channel and the operating mode and toread the results.The digital part of the chip uses triple redundancy toinsure protection against SEU effects.The global layout of the DCU is shown in Figure 4where the analogue core of the ADC, the digital blocksand the band-gap voltage reference are put in evidence.Figure 4: DCU layoutIII. TEST RESULTSA custom test-board for the DCU A/D converterprototype has been developed. It is based on acommercial micro-controller (Microchip PIC16F877)which interfaces via an I2C link the device under test(DUT) and a 20-bit resolution D/A converter used togenerate the input voltages for the DUT. Two 16-bitresolution A/D converters are used as measurementreferences, one for the LIR mode and the other for theHIR mode. The micro-controller is connected to a hostPC via a standard RS232 interface. A schematic blockdiagram of the test-board and a picture of the whole test-setup are shown in Figure 5 and in Figure 6, respectively.Figure 5: DCU test-board block diagramFigure 6: DCU test setupAll the digital functions of the IC have beensuccessfully tested.The A/D converter parameters like gain, Integral Non-Linearity (INL), Differential Non-Linearity (DNL) andTransition Noise (TN) RMS, have been measured for thetwo operating modes on all of the input channels. Theevaluation and characterisation tests were automatedusing specific test programs running in the micro-controller. The test results were read from the microcontrolled after completion via the RS232 interface.A sequence of 128 input voltages has been applied inthe two input ranges GND→1.25V in the LIR mode and1.25V→VDD in the HIR mode. In both operating modesthe gain is between 2.18 and 2.20 LSB/mV correspondingto a resolution of 500uV/LSB.Figure 7 shows the A/D INL for input voltages in the0 to 1.25V range (LIR). The periodic “saw-tooth” shapeobserved in the picture reveals no intrinsic ADC non-linearity over this range, where the INL is less than 1 LSBaccording to the specifications. If the extended range, 0 to2.5 V, is taken, the non-linearity due to limited commonmode range of the comparator is revealed as can be seenfrom Figure 8Figure 7: ADC INL in the LIR mode (input range =GND→1.25V)Figure 8: ADC INL in the LIR mode (input range =GND→VDD)The differential (Figure 9) non-linearity has beenevaluated and reveals a monotonic A/D convertercharacteristic and no missing codes.Valid workingrange ( in LIRmode)Figure 9: ADC DNL in the LIR mode (input range =GND→1.25V)Finally, 1024 samples of a fixed voltage were taken toevaluate the internal A/D noise (transition noise). FromFigure 10 it can be concluded that the transition noise hasan RMS value smaller than one LSB. The RMS of thetransition noise can be evaluated applying a sequence ofvery small voltage steps to the ADC input and evaluatingthe steepness of the transition between two adjacent ADCoutputs. This analysis leads to an noise RMS around 0.25LSB.Figure 10: ADC output distribution for a fixed inputvoltagePower dissipation has been evaluated: with the ADCworking at the maximum acquisition rate: the absorbedpower is less than 40mW. A preliminary ADCtemperature characterisation shows no significant changesin ADC performance with temperature.Several samples of the A/D converter have beenirradiated with X-rays up to 10 Mrad (dose rate 25Krad/min). No changes in the INL and in the transitionnoise have been observed. A gain decrease of0.4% / Mrad with the irradiation dose has been measured(see Figure 11).Figure 11 : A/D converter gain as a function of the doseIV. SUMMARYAs part of the CMS tracker slow control system, amixed-mode ASIC has been developed to monitor thedetector leakage currents, temperatures and power supplyvoltages. The IC has been implemented in a commercialsub-micron technology using a special set of layoutdesign rules to guarantee the level of radiation tolerancerequired in the LHC environment. The main buildingblock of this IC is a 12-bit ADC whose characteristicshave been described in this work. The ASIC has beenirradiated with X-rays up to 10 Mrad with only minorchanges in the circuit performance.A second version of the IC including an integratedtemperature sensor has now been submitted forfabricationV. REFERENCES[1] CMS Technical Design Report, CERN/LHCC/98-6(1998)[2] I2C Bus Specification, Signetics (1992)[3] B.Razhavi, Principles of Data Conversion SystemDesign, IEEE Press (1995)

A rad-hard 8-channel 12-bit resolution ADC for slow control applications in the LHC environment

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