Arnold, L

Baudot, J

Bonnet, D

Coffin, J P

Germain, M

Gojak, C

Kuhn, C

Lutz, Jean Robert

Suire, C

Tarchini, A

CERN Document Server

CONTROL SYSTEM OF THE SILICON MICROSTRIP LAYER FOR THESTAR EXPERIMENTD.Bonnet, J.Baudot, J.R. Lutz, L.Arnold, J.P.Coffin, M.Germain, C.Gojak, C.Kuhn, C.Suire,A.Tarchini, IReS, Strasbourg, FranceAnd the group STAR at SUBATECH, Nantes, France, and the LEPSI, Strasbourg, France, and theSTAR collaborationAbstractThe Silicon Vertex Tracker (SVT) in the STARexperiment at RHIC makes use, in its outer layer, ofsilicon-strip detectors. This layer is a barrel of 320double-sided detectors. The 768 strips of each detector’sside are read out by 6 ALICE-128C analog front endchips. Those chips are remotely controlled, using a JTAGprotocol. Another chip, the COSTAR, has been designedto perform in situ front end measurements (temperature,low and high voltage supplies, detector's bias currents).The Operator Interface is a Sun workstation, runningEPICS. The Input Output Controller is a VME crate. TheLAN is Ethernet, using the TCP/IP protocol.1  INTRODUCTIONThe STAR experiment (Solenoid Tracker At Rhic) willtake place in the RHIC (Relativistic Heavy-Ion Collider)at BNL (Brookhaven National Laboratory USA) from theend of year 1999. The IReS (Institut de RechercheSubatomique at Strasbourg) in collaboration with thelaboratory Subatech (Nantes) is responsible for theconstruction of a part of the experiment : the double-sidedsilicon strips detector (SSD). This detector is expected tomeasure the particle track position within a precision ofabout 30 micrometers. It is composed of 320 detectionmodules, which include the silicon detector and the front-end electronics (Alice 128C chips). It will be installed inthe STAR experiment in the middle of the year 2000.This document will describe the control system of theSSD layer.2  ARCHITECTURE2.1 Description of the systemThe system can be divided in two part :• The slow control which purpose is to monitor the“slow” variables and parameters, essentiallytemperature and power supplies.• The detector control which is involved in theinitialization and calibration of the system, and theonline analysis.ANALOGOUTJTAGREADOUTCONTROLFRONT END ELECTRONICSCONTROLSYSTEMPOWERSUPPLIESADC ANDREADOUTBOARDSFE CHIPSALICE 128CCONTROL CHIPSCOSTARDAQONLINEANALYSISDETECTORFigure 1: Block diagram of the system2.2 HardwareVME Power SupplySUNStationProcessor BoardDigital I /O and  JTAGPower SupplyInterfaceHV50VLV+2V-2VLV+5VEPICSVxWorksFigure 2: HardwareA common design for the control of all parts of the STARDetector has been decided by the STAR collaboration(Fig. 2). Basically, the control system is composed of  aVME crate and a SUN workstation.The VME crate is composed of a processor board runningthe VxWorks operating system and several interfaceboards.The SUN workstation is the main user interface, runningEPICS.International Conference on Accelerator and Large Experimental Physics Control Systems627International Conference  Accel rator and L rge Experim ntal Physics Control Systems, 1999, Trieste, Italy3  SLOW CONTROL3.1 Monitored parametersThe monitored parameters can be divided in two sets :• The parameters measured by the COSTAR chip oneach front end hybrid (there are 640 hybrids).• The parameters measured by the power supplydevice. They are representative of one ladder (thereare 20 ladders)The table 1. shows the different slow control parameters.Parameters Measured by NumberTemperature COSTAR 640FEE voltage supplied COSTAR 1280Bias ring and guard ringcurrentsCOSTAR 1280Detector depletion voltage Power supply 20Detector leakage current Power supply 20FEE voltage Power supply 40FEE current Power supply 40Readout electronicsvoltagePower supply 20Readout electronicsCurrentPower supply 20Table 1. Monitored parameters3.2 The COSTAR chipA general purpose chip has been designed to do in situslow control measurements of JTAG operateddetectors[1]. This chip has been designed by the LEPSI(Laboratoire d’Electronique et de Physique des SystèmesInstrumentaux, Strasbourg, France), in collaboration withthe IReS (Strasbourg, France). It is implanted on thehybrid of the STAR-SSD modules and is able to performthe following measurements:• The temperature of the hybrid (measured by aprobe integrated inside the chip). This informationwill be useful for controlling the effectiveness of thecooling system. The range is 0°C to 80°C, with aresolution of  0.5°C.•  The supplied voltages on the hybrid. These valuescan be compared with the supplied voltages in theADC and readout boards (which are read throughthe sense lines of the power supplied devices) inorder to detect any failure on the power lines of eachhybrid (over current, short circuits, broken orresistive connection, etc.).•  The leakage currents of the bias and guard rings.This is carried out by measuring the voltage across aresistor inserted in the bias line of the hybrid. Thebias and guard ring current values give usinformation about the status of the detector.JTAGControlerfmax=20MHz4 inputsADC8 bits - 100ks/s4 inputsADC8 bits - 100ks/s4 outputsDAC8 bits - 1MHzVoltageReferencesADC ClockSelectorIOData RegisterIDRegisterReadoutReg.32bitsReadoutReg.32bitsDACReg.32bitsTemperature ProbeContrlReg1ContrlReg2DACoutDACoutDACoutDACoutAin0Ain1Ain2Ain3Ain4JTAG busExternal osc.Din(8) Dout(8) ID(4)Figure 3: Block diagram of COSTARThe architecture of the COSTAR is shown in Fig. 3. Thischip is composed of ADCs, DACs and a digital I/O partthat can be accessed through a JTAG bus. This allowsseveral tasks to be performed which are useful for theSlow Control :• Monitoring and control of analog parameters(through the ADCs and DACs). Up to five generalpurpose inputs and four general purpose outputs areavailable.• Monitoring and control of digital parameters. An8-bit input/output register is available for thispurpose.Amongst the eight ADC inputs available in the chip, threeare dedicated to the conversion of internal temperatureand supplied voltage values. The five others are externalinputs, and two of them can be used for the measurementof bias and guard ring currents. In this application, thedigital I/O and the DACs are not used.In order to communicate with the slow control, theCOSTAR uses the same JTAG bus as the Alice 128Cchips. The connection to this bus does not require anyadditional components.4  DETECTOR CONTROL4.1 The Alice 128C chipThe Alice 128C chip has been designed by the LEPSI incollaboration with the IReS [2].It is a 128 channels low power chip which contains allparts of the front end electronics : pre-amplifier, shaper,multiplexer, internal pulse generator, etc.All this parts can be remotely configured via a JTAG bus.This allows us to remotely control such parameters as theshaping time, gain, internal pulse generator level, etc.The table 2. shows the registers controlled by the JTAGbus in the Alice 128C.628Parameter Size (bits)Bias register (analog chain parameters) 56Pulse level 8Pulse generator selected channels 128Output multiplexer 258Output buffer power 1Readout Token Enable 1Table 2. Alice 128C registers4.2 Configuration settingOnce the run configuration has been decided, it has to setup the detector in the appropriate state. This involvescommunication with DAQ, slow control, and anysoftware/hardware required to operate the detector. Adatabase, with all the configuration parameters stored init, is read and the parameters initialized in the targetsystem.4.3 Online analysisDuring a run, some kind of raw data analysis has to becarried out, to check whether the response of the detectoris coherent. This online analysis should be made on afraction of the events, and the results should be displayedwith histograms on an online monitor screen.5 CONCLUSIONThe hardware used in this control system is now welldefined and has been tested during the characterization ofthe first prototype detection module (at CERN SPS andPS, September-October 1999).Most of the job to be done for now  concerns the softwarepart, i.e. :• EPICS drivers and user interface• Online analysis• Configuration database6 REFERENCES [1] J.D. Berst, C. Colledani, “COSTAR”, Costar NoteV0.1-Lepsi9904 – Laboratoire d’Electronique et dePhysique des Système Instrumentaux , April 99. [2] J.R. Lutz and al., “Electrical characterization ofALICE128C: a low power CMOS ASIC for thereadout of silicon strip detectors”, 4th Workshop onElectronics for LHC Experiments, Rome (Italy),September 1998.629

Control System of the Silicon Microstrip Layer for the STAR Experiment

Control System of the Silicon Microstrip Layer for the STAR Experiment

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