Dorfan, D

Dubbs, T

Gilchriese, M G D

Grillo, A A

Lozano, M

Seiden, A

Spencer, E

Spieler, H

Ullán, M

CERN Document Server

Low Dose Rate Effects And Ionization Radiation Tolerance Of The Atlas TrackerFront-End Electronics.M. Ullán1,3, D. Dorfan1, T. Dubbs1, A. A. Grillo1, E. Spencer1, A. Seiden1, H. Spieler2, M. Gilchriese2,M. Lozano31 Santa Cruz Institute for Particle Physics (SCIPP), University of California at  Santa Cruz, Santa Cruz, CA 95064, USAullan@scipp.ucsc.edu2 Lawrence Berkeley National Laboratory (LBNL), University of California at Berkeley, 1 Cyclotron Rd, Berkeley, California94720, USA3 Centro Nacional de Microelectrónica (CNM-CSIC), Campus UAB, 08193 Bellaterra, Barcelona, SpainAbstractIonization damage has been investigated in the ICdesigned for the readout of the detectors in the SemiconductorTracker (SCT) of the ATLAS experiment at the LHC, theABCD chip. The technology used in the fabrication has beenfound to be free from Low Dose Rate Effects which facilitatesthe studies of the radiation hardness of the chips.Other experiments have been done on individualtransistors in order to study the effects of temperature andannealing, and to get quantitative information and a betterunderstanding of these mechanisms. With this information,suitable irradiation experiments have been designed for thechips to obtain a better answer about the survivability of thesechips in the real conditions of the ATLAS detector.I. INTRODUCTIONThe specific characteristics of the silicon detectors to beused in the Inner Detector of the ATLAS experiment that willbe installed in the Large Hadron Collider (LHC) at CERN,together with the large amount of data required to beprocessed in a very short period of time, force the 'front-end'electronics designed to do this job to be placed very close tothe actual detectors. This means, in fact, that the ICs for theimmediate data acquisition and pre-processing of the signalscoming from the detectors will be working in the active areaof the experiment, very close to the collision point. The ICswill, therefore, be operated in a very harsh environment due tothe amount of radiation in that area.For this reason, radiation-hard microelectronictechnologies have to be used, and the radiation hardness of theICs should be verified previous to the installation in theexperiment. This is the framework of this work, in which theradiation hardness of the two bipolar microelectronictechnologies that have been proposed for the experiment isbeing evaluated, and the total ionization radiation damageexpected for the ICs measured.A basic approach to test the radiation hardness of the ICsdesigned for the experiment is, in principle, to irradiate themin a short period of time up to the total dose expected in thereal case, and then measure their performance to see if theirparameters remain within specs. The problem, however, isusually not so straightforward. In the last years it has beenreported that bipolar transistors can suffer more radiationdamage when irradiated at low rates than when irradiated athigh rates [1], [2]. This means that an irradiation experimentdone at higher dose rates than the actual rate canunderestimate the damage. These phenomena are called LowDose Rate Effects (LDRE) of the bipolar transistors.Therefore, a more conservative approach for the testwould be to irradiate the chips in the real conditions of theexperiment. Then we would have the damage in the real case.But this possibility, though achievable in some particularcases due to the lower doses involved, is not realistic in themajority of the high energy physics or astrophysicsapplications, in which the long term operations of theexperiments lead to high energy depositions during the wholelife of the experiment but still at very low dose rates.This is the case of the ATLAS experiment which isintended to operate for 10 years with a total expected energydeposition (considering the stopping periods) of 10Mrads(SiO2), but at a dose rate of 0.05 rads(SiO2)/s [3]. Inthese circumstances an experiment to check the radiationhardness of the chips in the real conditions would takeapproximately 6.5 years which is not practical.Many different approaches have been tried to test doserate effects on a bipolar technology, and late studies haveshown that high temperature irradiations at high dose ratescan mimic the effects of low dose rate irradiations [4]-[6], butno one approach has yet been presented which covers all thepossibilities and, therefore, there is still a lack of a universalhardness assurance approach for bipolar technologies.Nevertheless, it has been seen that these effects are stronglytechnology dependent which means that, in many cases, somedevices will not suffer from LDRE for the particularconditions of the experiment. In such cases the first approachdescribed above could be used for hardness assurance studies,avoiding a lot of trouble in complicated and long term LDREstudies.In this work, the ionization radiation hardness of the ICdesigned for the front-end readout of the detectors of theATLAS-SCT (ABCD chip) is evaluated  taking into accountthe possible presence of  Low Dose Rate Effect in thetechnology (DMILL).II. TESTING PLANFour experiments have been devised in order to study theLDRE in the DMILL technology and the ionization damagecharacteristics on it:i) Experiment 0, the sensitivity to LDRE of bothtechnologies is evaluated irradiating test structures at a widerange of dose rates, but only to a dose that is reasonablyachievable at the interesting low rates, 1 Mrad in our case.ii) Experiment A, after evaluating the sensitivity of thesetechnologies to LDRE, the actual value of these effects ismeasured for the total dose of interest, and the final damageon the transistors measured for the full total dose at the doserate of interest.iii) Experiment B, the test structures are irradiated at ahigh rate up to the total dose of interest and at differenttemperatures in order to identify an appropriate temperature(optimum temperature) for the accelerated tests which bestmimics the damage produced at a low rate irradiation.iv) Experiment C, Accelerated tests are carried out on theICs at high dose rate and up to the total dose of interest usingthe optimum temperature if necessary.III. EXPERIMENTAL PROCEDURESAll irradiations have been done using three different Co60sources which provide 1.2 and 1.3 MeV gamma radiationwhich is widely used in ionization damage studies. A Pb+Alshielding box has been used together with geometricalconsiderations in order to avoid dose enhancement effectsaccording to standards [7], [8], guaranteeing less than a 20%systematic error in the dosimetry. Thermoluminiscent devices(TLD) have been used, also according to standards [9], inorder to identify the irradiation positions for the different doserates, obtaining a statistical deviation of less than a 5%. Thedevices were kept biased during irradiation in order to becloser to the real life conditions and low mass materials havebeen used for the supporting boards. The temperature controlhas been provided via resistive tape heaters and liquid coolingfor actuators. Thermocouples and Resistance TemperatureDetectors (RTD) in physical contact to the chips were usedfor the measurements.The Gummel Plots and common emitter current gains (β)of the transistors have been extracted before and afterirradiation. Consecutive measurements have been made onevery transistor, right after the irradiation, and for severalweeks later until the annealing process has been completed.Two main parameters have been used to characterize thedamage produced by radiation [9]: the excess base currentdensity (∆Jb), defined as the difference between the basecurrent density before and after irradiation at a base-emittervoltage of 0.7 V; and the relative beta change (∆β%), definedas the difference in the common emitter current gain, at thesame base-emitter voltage (0.7 V), before and after irradiationnormalized to the one before irradiation. Temperature hasbeen controlled during the measurements to make sure that itstays within a ±2 °C margin. Still, a commonly usedcorrection for small temperature differences has been used forthe base current by applying a factor to the post irradiationvalue which is equal to the ratio between the pre and postirradiation value of the collector current (which is known notto be affected by radiation).Test structures containing sets of bipolar transistors fromthe same technology in which the ABCD [10] chip is madehave been used. Two different transistor sizes have been usedfor the irradiations and small differences have been seenbetween the radiation damage for each. The sizes of thetransistors tested are 1.2 µm x 1.2 µm for the “minimum”transistor and 1.2 µm x 10 µm, for the, so called, “primary”transistor.IV. EXPERIMENT 0: LDRE SENSITIVITYThe purpose of this experiment is to evaluate thesensitivity of the DMILL technology to LDRE. This first stepis extremely important because it has been seen that LDREare strongly technology-dependent, and in many cases aparticular technology can be free of them or at least theymight not show in the range of dose rates of interest of theexperiment. In those cases tests of radiation damage can bedone directly at high dose rates saving a lot of effort incomplicated LDRE studies.A first study of the annealing of the damage produced bythe radiation from the moment just following the irradiationand the damage measured after a certain time has been carriedout in order to be sure that these effects don’t interfere withthe effects produced by the low dose rates [11]. The resultsshow that, in all the cases, he annealing, if it appears, isbeneficial (the damage is reduced), stops after at most threeweeks, and can not be accounted for the differences in thedamage for different dose rates. In the following all the datapoints represents measurements taken at least three weeksafter irradiation.For this experiment the transistors have been irradiated ata very wide range of dose rates and all of them up to a totaldose of 1 Mrad(SiO2) in order to obtain data even for the verylow dose rates in a reasonable period of time. The dose rateschosen cover a range of 4 full decades and the values are:0.05, 0.28, 1.33, 31.1, 112, 575 rads(SiO2)/s.Figure 1: Excess base current density (∆Jb) versus dose rate forDMILL transistors from Experiment 0.Figure 2: Relative beta change (∆β%) versus dose rate for DMILLtransistors from Experiment 0.The results of this experiment are shown in Figure 1 andFigure 2 for the DMILL transistors, in which both excess basecurrent density (∆Jb) and relative beta change (∆β%) areshown versus dose rate, all for the same total dose of 1 Mrad.All the data points correspond to the final measurement afterannealing has been completed. It can be seen that there is noevidence of low dose rate effects in these transistors, or it isnegligible. Similar plots are shown in Fig. 3 and Fig. 4 for theCB2 transistors. It is clear in these plots that these transistorssuffer total dose effects showing appreciably more damage atlow dose rates.V. EXPERIMENT A: MAPPING OF THE DAMAGE VS.TOTAL DOSEIn view of the results from Experiment 0, two mainconsequences can be obtained. The first one is that it isnecessary to know if there are still no LDRE for the DMILLtechnology at higher doses; and the second one is that anestimation of the extent of these effects is necessary for theCB2 transistors.For both of these measurements long term, low dose rateirradiations should be done up to the total 10 Mrads and at0.05 r/s dose rate, which are the real conditions in ATLAS-SCT. These experiments are not realizable because theywould take too long to give results. A solution to the problemis to map out the damage on the transistors vs. the total dosetaking intermediate measurements of the damage forincreasing total doses up to 10 Mrads. This way one canperform low dose rate irradiations up to a certain achievabletotal dose and estimate the damage at the final total dose byextrapolation. Furthermore, one can see if irradiations done atdifferent dose rates lead to a “rigid” shift of the curves or, onthe contrary, they change the shape or slope of them. If thecurves suffer rigid shifts for different dose rates, we can beassured that the differences between low and high dose rateirradiations are maintained for high total doses.The conditions of the four different mapping experimentsthat have been performed for this purpose can be seen inTable 1.Table 1: Conditions of the four mapping experiments.In Figure 3 and Figure 4 we can see the results of theseexperiments in terms of the excess base current density andthe relative beta change. It can be seen that for all dose ratesthe excess base current density is linear vs. total dose for alogarithmic plot on both axis (dependency type: ∆Jb ∝(dose)a; a = constant). The relative beta change follows also alinear dependency with total dose but in this case for only alogarithmic abscissas axis (dependency type: ∆β ∝ log(dose)).It also can be seen that the graphs for all four irradiations areparallel, and in fact superposed, meaning that the damage isthe same for all transistors regardless of the dose rate and forthe whole range of doses, indicating that there are no LDREfor these transistors up to 10 Mrads.Figure 3: Excess base current density (∆Jb) versus dose rate forDMILL transistors from Experiment A.Figure 4: Relative beta change (∆β%) versus dose rate for DMILLtransistors from Experiment A.The results show that the figures for the total ionizationdamage of the bipolar transistors of the DMILL technologyare 8 x 10-10 A/cm2 for the excess base current density and-45% for the beta change, giving a final value of thetransistors current gain (for the emitter sizes used in theexperiments) around 90 to 125.VI. EXPERIMENT B: TEMPERATUREGiven the fact that Experiment A has demonstrated thatthe DMILL technology doesn’t suffer from LDRE at least upto the conditions of interest for ATLAS-SCT, it can beconcluded that accelerated tests are not necessary for thehardness assurance testing of the ABCD chip. Therefore it isnot necessary to find the optimum temperature for theseirradiations, which was the initial goal of Experiment B.Figure 5: Excess base current density (∆Jb) versus temperature forDMILL transistors from Experiment B.Figure 6: Relative beta change (∆β%) versus temperature forDMILL transistors from Experiment B.Nevertheless, a set of experiments at differenttemperatures has been carried out with the bipolar transistorsof this technology in order to obtain the variations of thedamage in the transistors for different temperatures ofirradiation. The actual working temperature of the chips in thereal ATLAS-SCT environment is not as yet fixed, and a lowoptimum (worst case) temperature with a sharp slope in thedamage at low temperatures would make the hardnessassurance testing more difficult.Different irradiations have been done of the bipolartransistors all of them up to the total ATLAS-SCT dose of 10Mrads and at a very high dose rate (575 rads/s). Thetemperatures used in the study have been: 11, 37, 57, 70, 91,and 110 °C.Figure 5 and Figure 6 show the results of Experiment Bfor the test structures of the DMILL technology. It can beseen that the worst case temperature  appears at around 90 °Cwhich is a high enough temperature for the slope to be smoothat low temperatures. Nevertheless, it can be seen that dedifferent in the damage for an irradiation done at the expectedactual working temperature of the ICs at the ATLAS-SCT (10°C), and an irradiation at room temperature is appreciable, andshould be taken into account in future irradiation tests of theABCD chips.VII. EXPERIMENT C: FINAL TESTThe Results from Experiment A and Experiment Bdemonstrate that the DMILL technology is free from LDRE atthe range of total doses and dose rates of interest in theATLAS-SCT experiment, and that the difference in thedamage for the actual operating temperature and roomtemperature is low. This results validates the previous highdose rate irradiation tests carried out by the collaboration withthat result that the ABCD chip remains under specificationsfor the total life of operation [12].Nevertheless, the actual ABCD chips have been irradiatedin order to obtain the figure the damage produced on them by10 Mrads of ionization radiation. The irradiations have beendone at high dose rate (575 rads/s), up to the total dose of 10Mrads and at room temperature. The results from theseirradiations are currently being analyzed.VIII. CONCLUSIONThe technology used in the fabrication of the ICs proposedfor the front-end readout of the ATLAS-SCT (DMILL) hasbeen tested for ionization damage and considering low doserate effects. The results show that this technology, used in thefabrication of the ABCD chip, does not suffer from LDRE, orat least by a negligible amount. This result indicates thatirradiations performed to test the radiation tolerance of the ICscan be done at high dose rates without underestimating thedamage to the chips. This will save much effort in long termirradiations or accelerated tests.The results also show that the variation of the damageproduced on the chips for different irradiation temperaturesare not very large for the range of low temperatures, but stillshould be considered if the chips are in the edge of theirsurvivability after the irradiation tests.Finally, the non-existence of LDRE in the DMILLtechnology validates and confirms the results of previousirradiation tests within the collaboration indicating that theABCD chip will remain under specifications after he 10 yearsof operation in the ATLAS-SCT environment.REFERENCES[1] E. W. Enlow, et al. “Response of Advanced BipolarProcesses to Ionizing Radiation”, IEEE Trans. onNuclear Science, V.38, 1342 (1991)[2] R. D. Schrimpf, “Recent Advances in UnderstandingTotal-Dose Effects in Bipolar Transistors”, IEEE Trans.on Nuclear Science, June 96, p. 787.[3] ATLAS Inner Detector Technical Design Report (TDR),CERN/LHCC/97-16/17, April 1997.[4] S.C. Witczac, et al., “Accelerated Tests for SimulatingLow Dose Rate Degradation of Lateral and SubstratePNP Bipolar Junction Transistors”, IEEE Trans NuclearScience, Dec. 96, pg. 3151.[5] O. Flament, et al., “Ionizing dose hardness assurancemethodology for qualification of a BiCMOS technologydedicated to high dose level applications”, IEEE Trans.Nuclear Science, Dec. 98, p. 1420.[6] S.C. Witczac, et al., “Hardness Assurance Testing ofBipolar Junction Transistors at Elevated IrradiationTemperatures”, IEEE Trans. Nuclear Science, Dec. 97,p. 1989.[7] “Minimizing Dosimetry Errors in Radiation HardnessTesting of Silicon Electronic Devices Using Co-60Sources”, Annual Book of ASTM Standards, AmericanSociety For Testing And Materials (ASTM), E 1249–93,1993.[8] “Standard Guide for Ionizing Radiation (Total Dose)Effects Testing of Semiconductor Devices”, AnnualBook of ASTM Standards, American Society ForTesting And Materials (ASTM), F 1892–98, Nov. 98.[9] “Application of Thermoluminiscence-Dosimetry (TLD)Systems for Determining Absorbed Dose in Radiation-Hardness Testing of Electronic Devices”, Annual Bookof ASTM Standards, American Society For Testing AndMaterials (ASTM), E668–97, 1997.[10] W. Dabrowski, et al. “Design and performance of theABCD chip for the binary readout of silicon stripdetectors in the ATLAS Semiconductor Tracker”, Proc.of 1999 IEEE Nuclear Science Symposium, Seattle,Washington, USA, Oct 1999.[11] D. Dorfan, et al. “Measurement of Dose RateDependence of Radiation Induced Damage to theCurrent Gain in Bipolar Transistors”, IEEE Trans. onNuclear Science, Dec. 99, p. 1884.[12] E. Chesi, et al. “Performance of a 128 Channel AnalogueFront-End Chip for Readout of Si Strip DetectorModules for LHC Experiments”, IEEE Trans. onNuclear Science, Aug. 00, p. 1434.

Low Dose Rate Effects and Ionization Radiation Tolerance of the ATLAS Tracker Front-End Electronics

Low Dose Rate Effects and Ionization Radiation Tolerance of the ATLAS Tracker Front-End Electronics

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