Bonnet, D

Brogna, A

Coffin, J P

Deptuch, G

Gojak, C

Hu-Guo, C

Lutz, Jean Robert

Tarchini, A

CERN Document Server

The HAL25 Front-End Chipfor the ALICE Silicon Strip DetectorsD. Bonnet, A. Brogna, J.P. Coffin, G. Deptuch, C. Gojak, C. Hu-Guo*, J.R. Lutz, A. TarchiniIReS (IN2P3-ULP), Strasbourg, FranceJ.D. Berst, G. Claus, C. ColledaniLEPSI (IN2P3-ULP), Strasbourg, France*Corresponding author Christine.hu@ires.in2p3.frAbstractThe HAL25 is a mixed low noise, low power consumptionand radiation hardened ASIC intended to read out theSilicon Strip Detectors (SSD) in the ALICE tracker. It isdesigned in a 0.25 micron CMOS process and isconceptually similar to a previous chip, ALICE128C. Itcontains 128 analogue channels, each consisting of apreamplifier, a shaper and a storage capacitor. Theanalogue data is sampled by an external logic signal andthen is serially read out through an analogue multiplexer.This voltage signal is converted into a differential currentsignal by a differential linearised transconductanceoutput buffer. A slow control complying with the JTAGprotocol was implemented to set up the circuit.IntroductionThe HAL25 is a mixed, analogue digital, ASIC designedfor read-out of Silicon Strip Detectors (SSD) in theALICE tracker. It is based on the ALICE first generationchip, ALICE128C [1]. The ALICE128C chipperformances were successfully maintained up to 50 kradof the ionising dose. It is now used in the SSD front-endselectronic of the STAR tracker.In order to maintain some safety margin in radiationenvironment a new circuit has been designed. It has beendemonstrated that commercial deep sub-micron CMOSprocesses exhibit intrinsic radiation tolerance [2]. HAL25has been designed in a 0.25 micron CMOS process. Inaddition special design techniques have been used to meetthe demands of low noise, low power consumption andradiation hardness required by the ALICE experiment.For the SSD layer, the ALICE experiment needs a readoutdevice having a very large dynamic range (+/- 13 MIPs)with a good linearity and an adjustable shaping time from1.4 µs to 2.2 µs. This is a challenge for such a circuitdesigned in a deep sub-micron process operated at only2.5 V which is the edge of the use of standard analoguedesign techniques.This paper explains the design of the chip. Since HAL25is still under evaluation, only preliminary results will begiven.HAL25 Block DiagramFigure 1 shows the circuit block diagram. HAL25contains 128 channels, each consisting of a preamplifier,a shaper and a capacitor to store the voltage signalproportional to the collected charge on a strip of a silicondetector. The data is sampled by an external logic signaland is read out at 10 MHz through an analoguemultiplexer. This voltage signal is converted to adifferential current signal by a differential linearisedtransconductance output buffer. The chip isprogrammable via the JTAG protocol which allows:• to set up a programmable bias generator which tunesthe parameter of the analogue chains;• to check analogue behaviour of the chip by injectingadjustable charges to the inputs of selected channelswith a programmable pulse generator ;• to perform the boundary scan.AN_OUTBIAS PULSEPULSEGENANAMUX127PULSEREG0127|||ANALOGUE CHANNELS|||0127POWERONREG0TEMPO<1:0>PULSEDAC<7:0>CurrentOutputBuffer127READOUTREG0JTAG CONTROLERBIAS DAC<79:0>BYPASS<0> BSR<5:0> ID<7:0> STATUS<7:0> POWER_ENA<0> TOKEN_ENA<0>AIN<127>AIN<0> OUTBUFCTRL<1:0>BIAS GENERATORSPULSEID<3:0>TRSTBPWRSTBTCKTDITMSTDOHOLDFSTRBTK_INRCLKTK_OUTGNDREFAnalogue Sig.LVDS Sig.CMOS Sig.+-Fig. 1 HAL25 block diagramTable 1 shows the main specificationsSpecificationInput range ± 13 MIPsENC ≤ 400 e-Readout rate 10 MHzPower ≤ 1mW / ChannelTuneable Shaping Time 1.4 µs  to 2.2 µsSingle power supply 0 – 2.5 VI.  PreamplifierThe preamplifier is a charge amplifier made from asingle-ended cascode amplifier with an NMOS inputtransistor dimensioned to meet the noise specification.The additional bias branch is used to increase the currentin the input transistor [3]. Figure 2 shows the preamplifierschematic.Fig. 2. Preamplifier schematicThe advantages of the circuit compared to a conventionalfolded cascode structure are as follows:• A 2.5 V single power supply voltage whichsimplifies power supply circuit. This is a strongrequirement from the ALICE experiment.• The drain current of the input transistor which is thesum of the current flowing in both bias branches.This improves power efficiency.Simulation shows that preamplifier has a gain of 10mV/MIP (24000 e-) and a power consumption of 225 µW.II.  ShaperThe ALICE experiment needs a front-end circuit having avery large dynamic range (±13 MIPs) with a goodlinearity and a shaping time adjustable from 1.4 to 2.2 µs.A conventional shaper using a transistor as a feedbackresistor (Fig. 3a) cannot satisfy the required dynamic andthe linearity range. A linearised source degenerateddifferential pair (Fig. 3b) is used as an active feedbackresistor. The details of the shaper are shown in figure 4.      Fig. 3a. Shaper A Fig. 3b. Shaper BThe active feedback circuit is a linearizedtransconductance amplifier with a very lowtransconductance value built with the differential pair M1,M2 transistors. Transistors M3, M4 are used for sourcedegeneration of the differential pair linearising itstransconductance. Transistors M5, M6 are currentsources. The M7 and M8 constitute the non-symmetricalactive load of the differential pair. The transconductancevalue of the feedback circuit depends on thetransconductance of M1, M2 and the value ofconductance gDS  of the transistors M3, M4 connected inparallel [4]. Because the transconductance value of thetransistors M1 and M2 depends on the bias current, it iseasy to change the total transconductance of the circuit.This means that the equivalent resistance, on the feedbackpath, can be varied by changing the bias current. Theoutput DC level of the shaper is fixed by Vdc.V dcINOUTV biasM1 M2M3M4M5 M6M7 M8VddgndISHACcCfCloadFig.4 Shaper schematicThe noise contribution from the active feedback dependsmainly on the bias current and the value of gm of M7. Inorder to reduce the noise of the circuit, the followingpoints are taken into account:• minimum bias current ;• minimum gm of M7.A PMOS inverter is chosen as an amplifier stage in theshaper because it is the simplest way to meet thespecification of the very long peaking time. Thisapproach is a trade off between the values of thecapacitors and the gm of the amplifier. The coupling andfeedback capacitors are 3 pF and 0.6 pF, respectively.The storage capacitor is 10 pF.Another advantage of this shaper is that its DC outputlevel is adjustable via M1. It is possible to tune differentvoltage values for positive and negative inputs in order toincrease dynamic range.The shaper has a power consumption of 65 and 130 µWcorresponding to the shaping time of 2.2 µs and 1.4 µsrespectively. The total front-end gain is 35 mV/MIP in ±13 MIPs range. A non linearity less than 3% is obtainedby simulation within ± 10 MIPs range. The simulatedENC of the front-end circuit is :ENC = 207 e- + 10 e- /pF for τs = 1.4 µsENC = 158 e- + 10 e- /pF for τs = 2.2 µsWhere τs is the peaking time.OUTCfV offsetIN CcCloadHoldIN OUTCfCcCloadHoldGmGmINOUTV bias1V bias2V bias3V bias4VddgndVPRECfThe signal is sampled on the storage capacitor by anexternal LVDS HOLD signal activated at τs with respectto the peaking time.III.  Analogue MultiplexerThe analogue multiplexer is made of 128 intermediatebuffers, two 128 bits shift registers (POWERON,READOUT) and two extra bits flip-flop cells (TEMPO)(Fig. 1). The readout is performed by injecting a tokenwhich is shifted through READOUT. TEMPO is used todelay by two clock pulses the injected token (TK_IN) inorder to switch “ON” the first two intermediate buffersbefore beginning the readout. POWERON controls thepower on and off of the intermediate buffers whileREADOUT controls the serial data transfer.Only 3 of 128 buffers are powered on at the same timeduring the readout cycle. They are the buffer Ncorresponding to the channel being read and two adjacentbuffers i.e. channels N-1 and N+1. At the same time thebuffer N-2 is switched off and the buffer N+2 is switchedon. This means only 4 buffers dissipate power during thereadout.The out going token (TK_OUT signal) is picked up twochannels before the end of the readout of a chip in orderto allow a daisy chaining of several HAL25 circuitswithout extra clock cycles. An asynchronous FASTCLEAR signal can reset the token and abort the cycle atany moment of the readout.The multiplexer can be set by JTAG in order to test asingle channel. This test is called “transparent mode”.With HOLD signal inactive, the analogue response of aninjected signal can be observed at the output of the chip.IV. Differential Current BufferFigure 5 shows the three main parts of the analogueoutput buffer:• Single ended to differential voltage converter;• Linearised transconductor;• Output voltage reference controller.From MUXVdcV-V+LinearisedTrans-conductorV levelcontrolVrefVrefVrefI+I-On chip200 Ω25 pF25 pFReadoutFig. 5. Output buffer block diagramThe current gain and the output DC level are adjustableby the programmable bias generator. Analogue output ofseveral chips can be connected in parallel. Only the chipselected to be read out drives the output lines. Theoutputs of the remaining chips are in a high impedancestate. Non selected chips have their output bufferspowered off in order to reduce the total powerconsumption. The voltage reference controller sets thequiescent output level. This allows to use a simplefloating input differential buffer outside the chip to pickup the signal.a. Single ended to differential voltage converterThe single ended to differential voltage converter has aunity gain. It is built with  three operational amplifiersand a resistive ladder. The common mode output signal ofthis stage is clamped to the internal reference DC level,Vdc, common to the shaper and the multiplexer.b. Linearised transconductorThe linear transconductor is based on the differential pairlinearised by the cross-coupled quad cell [5].2:1 1:2n:11:n1:n n:1IN+ IN-aIDCaIDC(n+1)IDC (n+1)IDC2.5112.5OUT2OUT1M1 M2M5M3 M4M6 M7MC2 MC1MC3MC4MN1MN2MN5MP4MP1MP3MN3 MN4MN6MP2BIASNBIASP55Fig. 6 Linearised transconductanceThe schematic of the transconductance element is shownin Fig. 6. Transistors M1-M4 form the cross-coupledquad cell, while M6 and M7 constitute the differentialpair. The bias current of the differential pair is deliveredby the cross-coupled quad cell through the M5 transistorand the current source MC1. The bias current of thedifferential pair has a quadratic dependence on thedifferential input voltage. The output current presents alinear dependence of the input signal by a careful choiceof the weighting factor n. The additional current gain isachieved on the cascade of current mirrors MN1-MN2with MP1-MP2 and MN3-MN4 and MP3-MP4. Theoutput has a gain of 175 µA/MIP at nominal bias.c. Output voltage reference controllerThe classical control of the quiescent output levels by acommon mode feedback circuitry with low pass signalfiltering was not possible because it has to be off whenthe chip is not selected. Another solution, using a dummytransconductance stage and a feed forward circuitry forreferencing the output of the buffer, was preferred (Fig.7). Both inputs of the dummy transconductor are fed withthe common mode signal and resulting not balancedoutput signal is assumed to be the same for the maincircuitry. The output of the dummy element is balancedby comparing its voltage level to the reference signal inthe error amplifier. As a result, a balanced voltage equalto the reference value Vref is established at the output ofthe dummy transconductor. The both outputs of maintransconductor are forced to the same value throughcurrent mirrors. This design is potentially sensitive tomismatches, thus special care was taken at the layoutlevel. An eventual mismatch in the output voltagequiescent level can be adjusted by changing Vref.VrefV-V+LinearisedTrans-conductorI+ I-DummyTrans-conductorVdcIref/2Iref1 1 1 1B1B21 1 1 1Fig. 7. Quiescent output level controllerV.  Bias Generators and Current ReferenceThe bias generators provide DC currents and voltages tobias accurately all the analogue parts. They consist ofnine 8 bit DACs. Each DAC is made of a JTAG register,current sources and when necessary a current to voltageconverters. The JTAG register consists of a shift registerand a shadow register designed with a majority votinglogic approach in order to prevent Single Event Upset(SEU).In the HAL25 chip, an internal current source providescurrent reference to the bias generators. It is designed tobe insensitive to a +/- 8% power supply variation. Toprevent poly-silicon resistor value variation (+/- 20%) dueto the process, the reference is adjustable by JTAG in 5steps from -15% to +15% around nominal value.VI.  Test Pulse GeneratorThis feature can test analogue channels by injectingadjustable charge pulses. The dynamic range for testpulse is more than +/-15 MIPs, enough to test the fulldynamic range of analogue channels. A programmablenumber of channels can be tested together.VII.  JTAG ControllerThe control interface of HAL25 complies with the JTAGIEEE 1149.1 standard. It allows the access to the registersin the chip, especially for setting the bias and switchingbetween the running and the test modes. These modes arethe pulse test, the transparent test and the boundary scanof the pads involved in the readout.After reset of the controller, the circuit is in the bypassstate. For JTAG this means that serial data can skip thecircuit with one extra JTAG clock cycle per bypassedcircuit. For the readout part the token passes directly fromthe previous to the next HAL25. An ID number can beread from the chip by setting 4 input pads.HAL25 Power ConsumptionThree types of power consumption can be calculated:• Power consumption per channel during acquisition:P (no read out) = 355 µW (τs =1.4 µs)P (no read out) =  290 µW (τs = 2.2 µs)• Power consumption per channel during readout:P (read out) = 750 µW (τs =1.4 µs)P (read out) = 680 µW (τs = 2.2 µs)• Mean power consumption per channel for a read outcycle of 1 ms:<P> = 360 µW (τs =1.4 µs)<P> = 265 µW (τs = 2.2 µs)HAL25 LayoutThe HAL25 has an area of 3.65 x11.90 mm2 (Fig. 8). The processhas 1 poly and 3 metal layers. Theenclosed gate geometry with guardring technique was used in thelayout to prevent post-irradiationleakage currents in NMOS channeltransistors.The I/O pad sizes and placementpitches were designed to bedirectly compatible with theexisting Tape Automated Bonding(TAB) technique. All the padsexcept  the power supply pads areprotected with diodes. Pads usedby the JTAG protocol are CMOSwhile the readout control padscomply with the LVDS standard.  Fig. 8. HAL25Circuit EvaluationEvaluation of HAL25 is underway. Several chips havebeen tested on a probe station. Correct functionality of thechip has been verified.Figure 9 shows output stream from channel 1 to channel128. A 1 MIP signal injected on one channel shows upclearly after the average channel pedestals have beensubtracted.Fig. 9 Output streamFigure 10 shows analogue pulse shapes at output buffer asa function of the injected charges.-0.8-0.6-0.4-0.200.20.40.60.80 5 10 15 20time (µs)output diff HAL25 (V) From +/- 2 to +/- 14 MIPsFig. 10 Output shapesA good linearity (<4%) has been obtained (Fig. 11)within ±10 MIPs range. This has good agreement with thesimulation results.-0.8-0.6-0.4-0.200.20.40.60.8-20 -10 0 10 20MIPsDifferential output of HAL25 (V)HAL25 outputFitFig. 11 Output of HAL25 as a function of the input MIPsConclusionA new mixed ASIC intended for read out of SSD in theALICE tracker has been designed in a deep submicronprocess. The correct functionality of the chip has beenverified.Further investigations planned with HAL25 will includemore detailed performance studies especially the yieldoptimisation and the irradiation tests.AcknowledgmentWe would like to acknowledge the technical support fromthe Microelectronics group at CERN. Thanks to PierreJARRON for his support, to Giovanni ANELLI andAngelo RIVETTI for their advises and helps.References[1] L. HEBRARD et al. ‘ALICE128C: A CMOS FullCustom ASIC for the Readout of Silicon Strip Detectorsin the ALICE Experiment’ Proceeding of the SixthWorkshop on the Electronics for LHC Experiments,Rome, Italy, September 1998.[2] G. Anelli ‘Conception et Caractérisation de CircuitsIntégrés Résistants aux Radiations pour les Détecteurs deParticules du LHC en Technologie CMOSSubmicroniques Profondes’, Ph.D. thesis, INPG,December, 2000.[3] A. Rivetti et al. ‘A Mixed-Signal ASIC for the SiliconDrift Detectors of the ALICE Experiment in a 0.25umCMOS’, Proceeding of the Sixth Workshop on theElectronics for LHC Experiments, Krakow, Poland,September 2000. [4] G. Deptuch et al. “15 MHz Elliptic OTA-C Filters in1.2 µm CMOS Technology”, in Proc. Mixed Design ofIntegrated Circuits and Systems MIXDES 1998, Lodz,Poland, pp. 243-248[5] A. Nedungadi, T.R. Viswanathan, “Design of LinearCMOS Transconductance Elements”, IEEE, Trans. onCircuits and Systems, vol. CAS-31, No. 10, Oct. 1984

The HAL25 Front-end chip for the ALICE Silicon Strip Detectors

The HAL25 Front-end chip for the ALICE Silicon Strip Detectors

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