Berglund, S R

Bohm, C

Jon-And, K

Klereborn, J

Ramstedt, M

Selldén, B

CERN Document Server

Production and Test of the ATLAS Hadronic Calorimeter DigitizerS. Berglund, C. Bohm, K. Jon-And, J. Klereborn, M. Ramstedt and B. SelldénStockholm University, Sweden October 2001mank@physto.seAbstractThe pre-production stage of the full-scale production ofthe ATLAS TileCal digitizer started during the summer2001. To be able to ensure full functionality and quality, athorough test scheme was developed.All components are radiation tested before start ofproduction. After mounting components all digitizer boardswill pass burn-in and tests in Stockholm. Custom designedsoftware ensures that full functionality is maintained. Arecord of the test results is stored in a repository accessiblevia Internet for future reference. Similar test software is laterused at the site of full electronics assembly in Clermont-Ferrand cross referencing their results with the test dataentries.I. INTRODUCTION A. The DigitizerStockholm University is responsible for design,manufacture and quality control of the digitizing unit of theATLAS Hadron Calorimeter [1]. The calorimeter is oftencalled TileCal because of its interleaved iron and scintillatingtiles. Heavy particles interact with the iron tiles and formshowers of charged particles that produce light in theadjacent scintillating tiles. This light is transferred to an arrayof PMTs via wave length shifting fibers. The PMTs and allthe front-end electronics are contained in so called drawers atthe base of the calorimeter modules. There are 32 or 45PMTs in a drawer depending of its position in the detector.The PMTs are connected to 3-in-1 cards [2] that shape andamplify the pulses. The 3-in-1 cards are in turn connected todigitizers that sample the pulses.Each digitizer board serves six 3-in-1 channels. There aretwo TileDMUs, a specially designed controller and readoutASIC, on each digitizer board. Data from the TileDMUs areread out via a G-link based interface board (Fig.1). The TTC-system [3] delivers timing and slow control to the interfaceboard via fibers. The TTC signal is then distributed to thedigitizer boards. A drawer contains eight or six digitizerboards depending on its placement in the detector with theinterface board placed in the middle. When a digitizer boardat the far end of the drawer is read out, data and TTC signalspass through lines with no active components onintermediate boards. Thus, any malfunctioning componentson a digitizer board will only corrupt its own data.interfaceTile_DMU Tile_DMUTTC-rx Tile_DMU Tile_DMUTTC-rx Tile_DMU Tile_DMUTTC-rx Tile_DMU Tile_DMUTTC-rxTile_DMUTTC-rxTile_DMU Tile_DMUTTC-rxTile_DMU Tile_DMUTTC-rxTile_DMU Tile_DMUTTC-rxTile_DMUoptical fibersinterface optical fibersRead-outTTC distributionFig. 1 The data flow along a chain of eight digitizer boardsThe main components of the digitizer board are theADCs, the TileDMUs and the TTCrx. The ADCs are ten bitsconverters. To provide an effective dynamic range of 16 bitsthere are two ADC channels per PMT channel digitizing thetwo signals from the 3-in-1 card. These are high and low gainsignals with an amplification ratio of 64.Data from all channels are stored temporarily in pipelinememories in the TileDMUs. When the first level triggervalidates an event the TileDMU will choose the appropriategain, according to the amplitude of the signal, format the dataand store it in a readout buffer. Functions for tests andcalibration are also part of the TileDMU.B. Production of the digitizerIn order to ensure the quality of the full production, thepre-production has been made as close to the real productionas possible including all steps: manufacture, mounting, burn-in, tests and logistics. All design is now almost completedand final manufacturer and assembly-company will soon bechosen. A few small design modifications will be made totake care of a yield problem that was discovered during pre-production when mounting a high-density surface connector.The production and the test routines will also be improved toimplement some additional features suggested by the pre-production experience. In the pre-production 86 boards were manufactured andassembled with a surprisingly high fault rate level of about35 %. The sources of these faults have been investigated andare to a large extent understood. About 20% failed due tobadly soldered data connectors. To fix this the connectorsurface mount pads will be modified. About 5% failed due tomalfunctioning TileDMUs. This number was expected sincethe TileDMUs of the pre-production were not fully testedbefore delivery. The remaining 10% failures are beinginvestigated in more detail. When this is done there will be afinal product readiness review (PRR) and the massproduction will start, most likely in November this year.II TESTSA. Test procedureTo ensure the quality and functionality of the digitizerboards, tests are made at several checkpoints along theproduction process. Components used on the board arerequired to be radiation tolerant and are tested according tothe ATLAS recommendations [4]. Unassembled boards arechecked for breaks and shorts at the board manufacturer.Functionality of the TileDMUs are tested before and afterpackaging i.e. just before they are sent for assembly. Aftermounting the components the boards will be superficiallytested before delivery to the burn-in and test facility atStockholm University. The burnt in boards are thoroughlytested and then sent to the drawer assembly plant atClermont-Ferrand for assembly and final tests.B. Test Bench SetupA test drawer has been set up for the purpose ofproduction tests. This set-up is quite similar to a finalATLAS drawer. A RIOII VME processor is used as readoutbuffer and a TTCvi module as a source of clocks and forconfiguration of the digitizer boards (Fig. 2). These tests areall controlled by RIOII software. The main electronic parts inthe test drawer are the 3-in-1 system, the digitizer boards andthe interface link board.Fig. 2 Schematic picture of the test bench components and signalflowC. Radiation TestsMost active components have been tested for radiationtolerance and the remaining tests will take place before thefinal PRR and start of production.According to ATLAS requirements the digitizer should,without damage, resist the following doses: 3.5 krad ionizingradiation and 2.3*101 2  1MeV eq neutrons/cm2.Corresponding numbers for components containing bipolarsare 17.5 krad and 2.3*1012. These figures include theappropriate safety factors. Tests for single event effects(SEE) [4] should also be performed. With one exception(TTCrx), none of the digitizer components have a formalspecification on radiation tolerance from the manufacturer.Several tests have therefore been made to select componentswith the best radiation tolerance, which also are acceptablefrom the price/performance point of view. During the processseveral types of components have been rejected.The full installation will contain around 22000 ADCs.About 40 samples from various batches have been radiatedup to 50 krad and a subsample even up to 100 krad. Ourresult is that all samples stand 30 krad and some even 100WorkstationRIOIITTCviLaser CrateTTC-signalDigitizer x4Digitizer x4Interface boardData (G-link)krad of ionizing radiation. 18 samples have been exposed to7.5*1012 1 MeV eq n/cm2 with no malfunction detected.Between 8 and 20 samples from each of the digitizerCMOS circuit have been exposed to 10 krad ionizingradiation and 5*1012 1 MeV eq n/cm2. No errors weredetected.Only one sample of the TileDMU (CMOS) has beentested with radiation levels as above. For that sample nomalfunction was detected. Eight more will be tested shortly.A special test bench that tests the TileDMU has beendeveloped for the study of transient errors.In the near future we plan to make SEE tests on systemlevel using a 170 MeV proton beam. Also here we need todevelop a dedicated test bench.D. Test of the PCBThe vendor will test non-assembled boards for circuitbreaks and short circuits. Faulty boards are rejected. Afterassembly the boards are visually inspected for obviousmistakes and tested for power short circuits. A superficialtest using a dedicated test bench, similar to the one that willbe used in the board SEE tests, is planned. A more thoroughtest is made after the burn in.E. Test of data and TTC connectorIn a drawer four digitizers are read out in a chain to theinterface board. Data from the TileDMU, and data and theTTC signals from boards further away from the interface willpass through a high-density surface mounted connector oneach digitizer board. A faulty connector can thereforegenerate errors when passing signals from another board.Before starting the full test procedure the connectors must bethoroughly tested. This will be done using three fullyfunctional boards as reference boards. The board to be testedis placed close to the interface board so all connector pins areused. This is not the most efficient method since one wouldlike to test more than one board at a time in the drawer. Bytesting the connector in a special connector test tool, muchtime can be saved. Such a tool is being developed.F. Functionality TestAfter burn-in and test of the data connector, thefunctionality of the entire board will be tested. The only wayto do this is to first configure the digitizers and the 3-in-1-system and then read out data. This is done simulating theTileCal front-end electronics environment. It can be difficultto identify the error in faulty boards by analyzing the datasince most components interact. However, if a board passesthe test this will guarantee that ATLAS functionality ismaintained [5].First of all the TTCrx is tested to verify that the properclocks are generated and that commands can be transferred tothe digitizers. The TTC single error and double error flags[3] are monitored to verify the TTC transmission quality.This test also verifies that the TileDMUs are able to read out.The next step is to exercise the TileDMU verifying thatall programming parameters can be set. The memory is testedwith different bit patterns. This is done using a test modewhere all data are generated internally.Test pulses are produced by the 3-in-1 system to verifythat none of the ADC bits are stuck at one or zero. Thepedestal RMS is then calculated to estimate the noise level.The pedestal levels are examined to determine whether acomponent adjustment is needed. An on-board DAC is usedto scan part of the dynamic range to determine the linearity.All readout is protected by data word parity and cyclicredundancy check. Errors are not accepted.G. History files and QC-SheetFor all digitizer boards the history of modifications, testdata and some characteristics are stored in a history file.These are auto-generated from the software and are stored inHTML/ASCII-format for accessibility. When a board haspassed all tests a quality control sheet is generated in HTML-format for easy access by the collaboration.H. SoftwareThe test software is split into two programs, theconfiguration and readout software (CRS) and the graphicaluser interface and analysis software (GUI). The CRS isrunning on the RIOII in the same crate as the TTCvi. Itcontrols the configuration of the digitizers and the 3-in-1system via the TTCvi and receives data from the digitizersvia an S-link PCI card attached to the RIOII. This part iscalled Coot-Boot. The GUI, called Baltazar, is running on aworkstation (e.g. Windows NT PC) communicating withCoot-Boot via TCP/IP. The idea behind Baltazar is toimplement a user-friendly interface making it easy to operatethe test bench after a short introduction. The softwareautomatically generates the history report files and makesthem accessible from WWW.The GUI is coded in JAVA to achieve platformindependence. JAVA is also easily available and welldocumented on the web. Baltazar has also been used asreference software in TileCal test-beam. The data analysis ismade by Baltazar requiring all data (~900kByte/run) to betransferred from Coot-Boot. This takes only a few seconds.The JAVA code makes the analysis sufficiently fast.III. CONCLUSIONSThe TilCal digitizer is soon ready for full production. Inorder to assure fully tested boards and a high productionyield many test procedures have been developed and insertedin different places along the production chain. This hasrequired the development of different hardware and softwaretest benches.However there are still a few tests that must be improved.This will be done before the final production.IV. ACKNOWLEDGEMENTSWe would like to thank J. Molnar and A. Fenyvesi fromAtomki in Debrecen for their help making the neutronirradiation of our components.V. REFERENCES1 ATLAS Tile Calorimeter Technical Design Report,CERN/LHCC 96-422 Front-end Electronics for the ATLAS Tile Calorimeter,K. Anderson, J. Pilcher, H. Sanders, F. Tang, S.Berglund, C. Bohm, S-O. Holmgren, K. Jon-And, G.Blanchot, M. Cavalli-Sforza, Proceedings of the FourthWorkshop on Electronics for LHC Experiments, Rome,1998, p.2393 http://www.cern.ch/TTC/intro.html4 Atlas policy on Radiation Tolerant Electronics, ATLASdocument no ATC-TE-QA-0001 21-July 005 The ATLAS Tile Calorimeter Digitizer, S. Berglund, C.Bohm, M. Engström, S.-O. Holmgren, K. Jon-And, J.Klereborn, B. Selldén, S. Silverstein, K. Andersson, A.Hocker, J. Pilcher, H. Sanders, F. Tang, H. Wu,Proceedings of the Fifth Workshop on Electronics forLHC Experiments, Snowmass, Colorado, 1999, p.2556 S-link: a Prototype of the ATLAS Read-out Link, E. vander Bij, O.Boyle, Z.Meggyesi, Fourth Workshop onElectronics for LHC Experiments, Rome 1998, p. 375.

Production and Test of the ATLAS Hadronic Calorimeter Digitizer

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