Cervelli, G

Marchioro, A

Moreira, P

Vasey, F

CERN Document Server

A Radiation Tolerant Laser Driver Array forOptical Transmission in the LHC ExperimentsGiovanni Cervelli, Alessandro Marchioro, Paulo Moreira, and Francois VaseyCERN, EP Division, 1211 Geneva 23, SwitzerlandGiovanni.Cervelli@cern.chAbstractA 3-way Laser Driver ASIC has been implemented indeep-submicron CMOS technology, according to the CMSTracker performance and rad-tolerance requirements. Whilebeing optimised for analogue operation, the full-custom IC isalso compatible with LVDS digital signalling. It will bedeployed for analogue and digital transmission in the 50.000fibre link of the Tracker. A combination of linearizationmethods allows achieving good analogue performance (8-bitequivalent dynamic range, with 250 MHz bandwidth), whilemaintaining wide input common-mode range (±350 mV) andpower dissipation of 10 mW/channel. The linearly amplifiedsignals are superposed to a DC-current, programmable over awide range (0-55 mA). The latter capability allows tracking ofchanges in laser threshold due to ageing or radiation damage.The driver gain and laser bias-current are programmable via aSEU-robust serial interface. The results of ASIC qualificationare discussed in the paper.I. INTRODUCTIONData connection to the CMS Tracker Front-Ends isprovided by a large number of optical fibre links: 50.000analogue for readout and 3.000 digital for trigger, timing, andcontrol signals distribution [1]. The Front-End componentsmust withstand the harsh radiation environment of theTracker, over the planned detector lifetime of 10 years (totalionising dose and hadron fluence exceeding 10 MRads and1014 neutron-equivalent/cm2 respectively) [2]. The baselinetechnology for ASIC developments in the Tracker is a0.25 µm CMOS, 3-metals, commercial technology (5 nmoxide thickness) [3, 4, 5]. The intrinsic radiation tolerance ofthis technology is increased to the required levels, by usingappropriately extended design-rules and self-correcting logic.The use of this technology for analogue applications wascarefully evaluated before employing it for the design of theFront End chips.A Linear Laser Driver (LLD) array for the CMS Trackerlinks had been already developed and implemented in a non-radiation tolerant BiCMOS technology [6]. The design wasthen translated in the 0.25 µm CMOS technology at an earlierstage of the Tracker design [7]. A new LLD has now beenimplemented in the same technology, appropriately matchingthe Tracker modularity and functionality requirements forboth analogue and digital links.Section II explains the device functionality and majorspecifications. Section III describes the electrical circuit andlayout. Section IV reports on the measurement results anddevice qualification.II. FUNCTIONALITYFigure 1 shows the block diagram of the new LLD chip.The laser driver converts a differential input voltage into asingle ended output current added to a pre-set DC current. TheDC current allows correct biasing of the laser diode abovethreshold in the linear region of its characteristic. Theabsolute value of the bias current can be varied over a widerange (0 to 55 mA), in order to maintain the correctfunctionality of laser diodes with very high threshold currentsas a consequence of radiation damage. The laser diode-biasingscheme (current sink) is compatible with the use of common-anode laser diode arrays.LD0 LD1 LD2+ + +-Idc0-Idc1-Idc2V0-V2+V2-V0+V1+V1-I2C Interfaceto lasersSCLSDAfrom MuxAdr (5)Reg (3)Bias(7)Gain (2)100 Ω100 Ω 100 ΩFigure 1: Block diagram.Input signals are transmitted to the laser driver using some0-30 cm of 100 Ω matched transmission lines. The driver isoptimised for analogue operation in terms of exhibiting goodlinearity and low noise. However, input voltage levels arecompatible with the digital LVDS standard (±400 mV into100 Ω). The gain can be chosen from 4 pre-set values. Gaincontrol provides an extra degree of freedom for optimallyequalising the CMS Tracker readout chain. A system-levelsimulation of the fibre link performance achievable with afour-gain equalisation is presented in [8].The IC modularity is 3 channels per chip. About 20thousand 3-way laser drivers will be used for the CMSTracker readout and control links. The total power dissipationof individual chips must remain constant regardless of themodulation signal to minimise cross-talk and noise injectionin the common power supplies.The channels can be individually addressed via a serialdigital interface (Philips Semiconductors I2C standard), whichallows individual power down, gain control, and pre-biascontrol. Robustness to Single Event Upsets is achieved bytripling the digital logic in the interface and by using amajority voting decision scheme. The power-up I2C registerconfiguration is read from a set of hard-wired inputs. Thus itis possible to insure that the optical links are correctly biasedat power-up.III. CIRCUIT AND LAYOUTThe Linear Laser Driver consists of a Linear Driver and alaser-diode bias generator (Figure 2).Vdd VddV1 V2I2I1rVddVss VssVss VssVssVddVddgaincontrolgaincontrolVsssinkI1-I2 IOUTactivebulkdummyoutputFigure 2: Circuit diagram.The Linear Driver consists of a degenerated PMOSdifferential pair and a push-pull output stage. The degenerateddifferential pair, in comparison to alternative solutions, isconceptually simple and offers good dynamic and noiseperformance with limited power dissipation. The PMOSversion is bulk-effect-free, thus allowing a larger inputcommon-mode range. The required linearity is obtained bycombining two source-degeneration methods: a parallelsource-degeneration resistor, and a source-bulk cross-connection between the transistors of the differential pair. Theuse of both methods allows keeping the degeneration resistorto a value compatible with the required input common-moderange. The push-pull output stage mirrors the currents in thedifferential pair branches and subtract them at the outputnode. Three switched output stages can be activated inparallel, to provide four different selectable gains. In order tokeep the power supply current constant, a dummy outputstage dumps the complement of the modulation currentdirectly into the power supplies.The laser-diode bias generator circuit consists of an arrayof current sources and sinks. The enabling logic allows themto be switched on and off as appropriate in order to generate acurrent linearly variable between 0 and 55 mA. A regulatedcascode scheme [9] has been used to keep the outputimpedance high and the compliance voltage low (<500 mV)in all possible operating conditions. To minimise the crosstalk within a given chip, each individual channel contains itsown independent bias circuit and power-down logic.The circuit has been laid-out taking particular care ofmatching the differential pairs, the current mirrors, and theelementary current sources and sinks. All the NMOStransistors have enclosed geometry and isolation guard-ringsto prevent the formation of radiation-induced leakagechannels between source and drain in a same transistor orbetween adjacent transistors. These layout practices, togetherwith the intrinsic good quality of the gate oxide of thetechnology being used, offer proven radiation tolerance up tolevels compatible with the most stringent requirements ofHEP experiments. The Linear Laser Driver layout and pin-outare shown in Figure 3.I2out   VDD   VSS   I1out   VDD   VSS   I0out   VDDV2+    V2-    VDD    V1+    V1-    VSS    V0+    V0-I2CA2I2CA3I2CA4I2CA5I2CA6DRES6VDDVSSPONbRESbSDASCLDRES4DRES5VDDVSSFigure 3: Device layout (die size: 2 mm x 2 mm).IV. DEVICE QUALIFICATIONThe LLD static and dynamic performance has been testedextensively, for different chips and various settings of theirconfiguration registers (different gains and bias currents).Moreover, the foundry provided us with prototype chipscorresponding to 5 different process corners. This practice isused to evaluate the deviation between the expected andactual performance in the final production lot due to statisticalprocess variations. Twelve chips corresponding to 5 differentprocess corners have been mounted and tested and shown tobe fully functional. Channel-to-channel as well as chip-to-chip variation appears to be very limited (regardless of thedifferent processing). One chip (nominal process) has beentested for tolerance to total-dose radiation and acceleratedageing. The set of qualification results is presented in thefollowing sub-sections.A. Static performanceFigure 4 shows the pre-bias current for 5 chips differentlyprocessed (different σs). The measured LSB is 0.45 mA andthe highest current that can be generated on-chip is 57 mA.The transfer characteristics (differential and common-mode)and output characteristic of the LLD have been measured witha Semiconductor Parameter Analyser. Figure 5 shows thedifferential transfer characteristics of the LLD, for fourdifferent gains (and different σs). The measured(transconductance) gain values are 5.3 mS, 7.7 mS, 10.6 mS,and 13.2 mS (5% above their nominal design values).0 16 32 48 64 80 96 112 1280102030405060I2C REGISTERPRE-BIAS CURRENT [mA]σ = -3.0σ = -1.5σ = 0σ = +1.5σ = 3.0Figure 4: Pre-bias current.-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-10 -8 -6 -4 -2  0  2  4  6  8 10DIFFERENTIAL INPUT VOLTAGE [V]MODULATION CURRENT [mA]GAIN = 5mSGAIN = 7.5mSGAIN = 10mSGAIN = 12.5mSFigure 5: Differential transfer characteristic.Figure 6 shows the linearity error, for different inputcommon mode voltages (Vcm = 0 and Vcm = ±625 mV). Thelinearity error is calculated as the absolute difference betweenthe real output current and its (least-square) linear fit, and isexpressed as a percentage of the specified operating range(integral linearity deviation). In absence of common mode,the error is less than 0.5% over the whole linear operatingrange (±300 mV). The common-mode has an impact onlinearity. However, performance degradation is negligible foran input common mode between ±350 mV. Figure 7 showsthe integral linearity deviation as a function of the inputcommon mode.-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25-2-1.5-1-0.500.511.52DIFFERENTIAL INPUT VOLTAGE [V]INTEGRAL LINEARITY DEVIATION [%]VCM = -625mVVCM = 0VVCM = +625mVFigure 6: Linearity error.-0.75 -0.625 -0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 0.5 0.625 0.7500.511.522.53COMMON MODE INPUT VOLTAGE [V]INTEGRAL LINEARITY DEVIATION [%]σ = -3.0σ = -1.5σ = 0σ = +1.5σ = +3.0Figure 7: Common-mode impact on linearity error.The Common Mode Rejection Ratio at DC is inferredfrom the common-mode transfer characteristic. The DC-CMRR is 40 dB in the worst case (maximum laser-bias) andbecomes as high as 70 dB at low biases. The outputimpedance (inferred from the output characteristic) of theLLD varies between 3 kΩ and 10 kΩ, depending on the pre-bias, and is in all cases much higher than the typical dynamicimpedance of the laser diode (<10 Ω).The minimum power consumption is 10mW per channel atminimum bias and minimum gain. The power consumptionincreases proportionally to the bias current and it is also tosome extent dependent on the gain. The maximum powerconsumption is below 110 mW/channel.B. Dynamic performanceThe dynamic performance of the LLD has been evaluatedwith laser emitters, which are representative of the ones to beused in the final application. A wide-bandwidth optical headis used for receiving the optical signal and converting it backto electrical for compatibility with standard instrumentation.The pulse response of different chips and for different gains isshown in Figure 8. The response exhibits little overshoot andringing. The measured rise and fall times are below 2.5 ns.The measured settling times (to within 1% of the final value)are of 10-12 ns, which leaves (for a 40 MHz sampled system)13-15 ns for correctly sampling the output signal.-5 0 5 10 15 20 25 30 35 40 45-2024681012x 10-3TIME [ns]OUTPUT VOLTAGE [V]GAIN = 5mSGAIN = 7.5mSGAIN = 10mSGAIN = 12.5mSFigure 8: Pulse response.The frequency responses (differential and common-mode)are shown in Figure 9. The analogue bandwidth has beenmeasured with a network analyser and was found to be250 MHz. The equivalent input noise into this bandwidth isgain and laser bias dependent. The measured noise is in allcases below 1 mVrms. The CMRR is shown in Figure 10 as afunction of frequency (15 mA bias current). Cross-talkbetween channels has been also measured and is below –60 dB.101 102-90-80-70-60-50-40-30FREQUENCY [MHz]TRANSFER FUNCTION [dB]GAIN = 5mSGAIN = 7.5mSGAIN = 10mSGAIN = 12.5mSFigure 9: Frequency response.101 102-5051015202530354045FREQUENCY [MHz]CMRR [dB]GAIN = 5mSGAIN = 7.5mSGAIN = 10mSGAIN = 12.5mSFigure 10: Common Mode Rejection Ratio.C. Radiation hardnessThe circuit has been tested for total ionising dose effectsusing an X-ray source, to investigate possible performancedegradation related to ionising effects (charge trapping inoxide interface states). The experiment has been carried outaccording to ESA/SCC recommendation for IC qualificationwith respect to total dose effects [10]. The chip has beenirradiated in three steps to 1 Mrad, 10 Mrad and 20 MRad(SiO2), at a constant dose rate of 21.2 Krad/min. Afterirradiation the chip was annealed for 24 hours at roomtemperature, followed by 168 hours at 100°C (acceleratedlife). The full set of static measurements was carried out aftereach step in order to assess any change in performance. Thechip was under nominal bias during irradiation with the threechannels switched on at maximum pre-bias.The results of radiation and accelerated life testing showthat the LLD will operate within specifications all during theexperiment lifetime (10 years). The overall radiation effectsare negligible or acceptable. The laser-bias current shows anincrease of 5%, 10% and 15% for three different channels inthe same chip (see Figure 11).0 16 32 48 64 80 96 112 128010203040506070I2C REGISTERPRE-BIAS CURRENT [mA]0Rads1MRads10MRads20MRads24h @ 25°C168h @ 100°CFigure 11: Pre-bias during irradiation.This is attributed to the NMOS type VT-referred currentreference and is compatible with the previously measuredthreshold variations in NMOS devices. There is no significantchange in the LLD differential or common-mode transfercharacteristics nor in the output characteristics.The LLD robustness to SEU needs to be tested and anexperiment is being planned before the end of the year.V. CONCLUSIONSA Linear Laser Driver array has been developed andimplemented in a commercially available 0.25 µm CMOStechnology. The device has been designed to comply with thestringent CMS requirements for analogue optical transmissionin the Tracker readout. It is however also compatible withdigital optical transmission modes in the Tracker slow controlsystem. Sample devices have been tested and shown to befully functional. The switched gains can be used to equalisethe significant insertion loss spread expected from the 50.000analogue optical links. The pre-bias current is programmableover a wide range, with 7-bit resolution, allowing tracking ofoptical source degradation during detector lifetime. The LLDarray has a modularity of three channels. However, since thechannels can be individually disabled any modularity belowthat can also be chosen without a power penalty. Theextensive set of measurements showed that the devicematches or exceeds the required analogue performance.Integral linearity deviation is better than 0.5% over an inputcommon mode range of ±350 mV. Input referred noise is lessthan 1 mV in an analogue bandwidth of 250 MHz. Powerdissipation at maximum pre-bias is below 110 mW perchannel. The radiation testing of one device showed that theanalogue performance would also be maintained after a totalionising dose comparable with the one expected during theexperiment lifetime. The parameters spread and yield for thetested devices are very good. Twelve devices have been testedand shown to be fully functional. The new chips will bepackaged in a 5 mm x 5 mm LPCC case for ease of testingand installation in the Tracker readout and control hybrids.VI. ACKNOWLEDGEMENTSThe precious contribution to this work from GulrukhKattakh of Peshawar University, Pakistan, and from RobertGrabit and Cristophe Sigaud of CERN, Geneva, isacknowledged.VII. REFERENCES[1] F. Vasey, V. Arbet-Engels, J. Batten et al., Developmentof radiation-hard optical links for the CMS tracker atCERN, IEEE Transactions on Nuclear Science (NSS1997 Proceedings), Vol. 45, No. 3, 1998, pp. 331-337.[2] CMS Collaboration, The Tracker Project, TechnicalDesign Report, CERN/LHCC/98-6, 1998.[3] A. Rivetti, G. Anelli, F. Anghinolfi et al., Analog Designin Deep Sub-micron CMOS Processes for LHC,Proceedings of the Fifth workshop on electronics forLHC experiments, CERN/LHCC/99-33, Snowmass,1999, pp. 157-161.[4] P. Jarron, G. Anelli, T. Calin et al., Deep sub-micronCMOS technologies for the LHC experiments, NuclearPhysics B (Proceedings Supplements), Vol. 78, 1999, pp.625-634.[5] G.Anelli et al., “Radiation tolerant VLSI circuits instandard deep-submicron CMOS technologies for theLHC experiments: practical design aspects”, IEEETransactions on Nuclear Science, Vol. 46, No. 6, 1999.[6] A. Marchioro, P. Moreira, T. Toifl and T. Vaaraniemi,An integrated laser driver array for analogue datatransmission in the LHC experiments, Proceedings ofthe Third workshop on electronics for LHC experiments,CERN/LHCC/97-60, London, 1997, pp. 282-286.[7] G. Cervelli, A. Marchioro, P. Moreira, F. Vasey, Alinear laser driver array for optical transmission in LHCeperiments, 2000 IEEE Nuclear Science SymposiumConference Record, Lyon, October 2000.[8] T.Bauer, F.Vasey, A Model for the CMS TrackerAnalog Optical Link, CMS NOTE 2000/056, September2000.[9] E. Säckinger, W. Guggenbühl, A high-swing high-impedance MOS cascode circuit, IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, February 1990.[10] Total Dose Steady-State Irradiation Test Method,ESA/SCC (European Space Agency / SpaceComponents Co-ordination Group), Basic SpecificationsNo. 22900, Draft Issue 5, July 1993.

A Radiation Tolerant Laser Driver Array for Optical Transmission in the LHC Experiments

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